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A novel gate first integration approach enabling ultra low-EOT is demonstrated. HfO2 based devices with a zero interface layer and optimized gate-electrode is used to achieve EOT and Tinv values of ˜5 Å and ˜8 Å respectively for both n and pMOS devices. The drive currents at Ioff=100 nA/μm with VDD=1 V is 1.4 mA/μm and 0.6 mA/μm (no SiGe source/drain) for n and pMOS respectively. The technology further...
The large negative Vfb shift by capping a thin layer of Me2O3 (Me= Gd, Y or Dy) on SiO2 and HfO2 with TaN metal gate was investigated. It was found that the negative Vfb shift is due to the dipole formation at MeSiO-SiO2 interface. The local bonding asymmetry is proposed to be the underlying reason for the dipole formation.
We discuss several advancements over our previous report (S. Kubicek, 2006): - Introduction of conventional stress boosters resulting in 16% and 11% for nMOS and pMOS respectively. For the first time the compatibility of SMT (stress memorization technique) with high-kappa/metal gate is demonstrated. In addition, we developed a blanket SMT process that does not require a photo to protect the pMOS by...
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