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In this paper, a 28nm radio frequency (RF) complementary metal-oxide-semiconductor (CMOS) power amplifier (PA) is presented. It was designed to meet 3GPP TS 36.101 V10.10.0 requirements for Long Term Evolution (LTE). The design was tested on board and has full onchip matching. Furthermore, the biasing for class-AB is also implemented on chip. The maximum gain is more than 15 dB until 0dBm input power...
In 60 GHz radios, at least 9 GHz flat gain is needed for the whole band for 16-QAM modulation. A 23 GHz 3 dB bandwidth, 6.3 dB to 17.5 dB variable gain, less than 4.3 dB NF, −7.7 dBm IIP3, four-stage common source LNA is proposed in this paper. The LNA uses guided micro-strip transmission line to realize simple input and inter-stage impedance matching networks. The prototype LNA is implemented in...
This paper presents a double-balanced CMOS down-conversion mixer for 60-GHz receivers, although the mixer is designed specifically for a phased array receiver architecture. The proposed mixer uses two on-chip baluns implemented with the two top metal layers in a 0.13-μm CMOS technology. The baluns provide 180° differential outputs from applied single-ended input at the radio-frequency (RF) and local-oscillator...
This paper discusses the design of a 60 GHz low noise amplifier (LNA) using a standard low power SOI CMOS process from ST Microelectronics. First, we outline the technology as well as the mm-wave design challenges. Using recent work on coplanar waveguide (CPW) modeling, we describe how it's possible to use parametric, 3D electromagnetic simulation to complete or replace analytical models of on-chip...
A 53 dB gain limiting amplifier for OC-192 and 10 GbE applications is developed in a 50 GHz fT SiGe SOI complimentary bipolar process, and has 5 mV pk-pk sensitivity, 1.25 V pk-pk maximum input signal, 14 ps (20/80%) rise/fall times and 450 mV pk-pk output into matched differential 50 Ohm loads, consuming 430 mW on a 3.3 V supply. Input Cherry-Hooper gain stages limit the -3 dB bandwidth to 11 GHz...
A high intercept points, cost-effective, and power-efficient switching FET double balanced mixer (DBM) is reported. The Switching FET DBM demonstrated in this work offers input intercept points (IIP3) and conversion loss typically 44 dBm and 8.5 dB respectively with 15 dBm LO power for the frequency band (RF: 900-2150 MHz, LO: 850-1950 MHz, IF: 50-200 MHz). The measured interport isolation is typically...
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