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Due to their reconfigurability and their high density of resources, SRAM-based FPGAs are more and more used in embedded systems. For some applications (Pay-TV,Banking, Telecommunication ...), a high level of security is needed. FPGAs are intrinsically sensitive to ionizing effects, such as light stimulation, and attackers can try to exploit faults injected in the downloaded configuration. Previous...
Networks on chips (NoCs) provide a mechanism for handling complex communications in the next generation of integrated circuits. At the same time, lower yield in nano-technology, makes self repair communication channels a necessity in design of digital systems. This paper proposes a reliable NoC architecture based on specific application mapped onto an NoC. This architecture is capable of recovering...
In this paper, we present a new technique to improve the reliability of H-tree SRAM memories. This technique deals with the SRAM power-bus monitoring by using built-in current sensor (BICS) circuits that detect abnormal current dissipation in the memory power-bus. This abnormal current is the result of a single-event upset (SEU) in the memory and it is generated during the inversion of the state of...
This paper describes hybrid-redundant design of monitoring systems with proprietary industrial-control computer boards. Input channels use three-mode redundancy, host controllers two-mode redundancy and output channels use warm redundancy. Experiments and analysis of system reliability by the Markov model indicate that the reliability of normal operation for 5 years is above 0.9.
The automata roots of path sensitizing fault diagnosis are discussed. It is demonstrated that the path sensitizing diagnosis method is equivalent to a Moore type "machine identification" experiment for a machine class which contains good and faulty copies of a transmission path submachine of a complete machine. The maximum length of a complete set of path sensitizing tests for a machine...
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