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We describe the methodology; the design and the implementation of scheduler block of interconnect. The scheduler block is implemented in Verilog using SYNOPSYS tool's DVE and Design_vision. The interconnect is capable of handling 72 bit packets and a total of 32 packets at a time. There are total 8 devices and we have to establish the communication between them. Each device consists of an input block...
The design plan and HSPICE measurement of a high acquisition speed for a sample of 8-bit CMOS differential successive approximation register (SAR) Analog-to-digital converter (ADC) are presented. The operation of the conventional main switch-capacitor array is divided into two switch-capacitor arrays. Such that, one switched-capacitor array is used to define the four most-significant bits, while the...
This article discussed about modeling of uCOS real time operation system kernel which is widely used in embedded system field based on CSP, describing the behavior of uCOS from the higher abstract layer, to help us understand how uCOS working better, also provide foundation of further working on uCOS includes model checking and soundness verification on uCOS. This article focused on the task scheduling...
A two-dimensionally (2-D) scanning array employing a planar switched beam network (SBN) is proposed for 60-GHz high data rate wireless communication. SBNs offer a number of advantages including low cost, multibeam operation, simple direction finding, and minimal power consumption. Unlike existing switched beam arrays operating at 60 GHz, the proposed array scans in both planes. Also, in contrast to...
Photovoltaic power supplied to the utility grid is gaining more and more visibility while the world's power demand is increases. Growing demand, advancements in semiconductor technology and magnetic materials such as high frequency inductor cores, has a significant impact on PV inverter topologies and their efficiencies, on the improvement of the control circuits on the potential of costs reduction...
In this paper, we developed a photovoltaic array reconfiguration algorithm to maximize the power that an array can provide a load. The algorithm reconfigures the array such that each element of the array is operated at its maximum power point. A switch topology was also designed to implement the algorithm using the minimum number of switches. Two parameters are used by the algorithm: array loaded...
This paper describes the design and realization of a 4??4 Butler matrix as a beam forming network along with 4 linear antenna arrays to obtain four steerable beams, operating at 2.4 GHz. The simulation results are obtained using FEKO software. Further the concept of multibeam switching is discussed with an idea of suspended feed in between two matrices.
In recent years, many researchers have proposed the usage of molecular scale devices exhibiting negative differential resistance (NDR) in the realization of programmable logic circuitry. This paper deals with the utilization of one such system built from NDR based circuitry, specifically the Goto pair, in the implementation of a programmable threshold logic array (PTLA). Furthermore, the PTLA considered...
A 10-bit successive approximation analog-to-digital converter (ADC), with offset correction circuitry and a tunable series attenuation capacitor is presented for implantable biosensor applications. The ADC is designed in a standard 0.13 ??m CMOS process technology and can operate with supply voltages down to 0.6 V. The ADC uses MOSFETs that are designed to operate in the sub-threshold region of operation...
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