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Firewalls, key components for secured network infrastructures, are faced with two different kinds of challenges: first, they must be fast enough to classify network packets at line speed, and second, their packet processing capabilities should be versatile in order to support complex filtering policies. Unfortunately, most existing classification systems do not qualify equally well for both requirements:...
Data compression technology is the necessary technology in the age of big data. Compared with software compression techniques, hardware compression techniques can improve speed and reduce power consumption. LZMA is a lossless compression technology, and its hardware implementation has broad application prospects. This paper proposes a novel high-performance implementation of the LZMA compression algorithm...
Genetic sequence alignment has always been a computational challenge in bioinformatics. Depending on the problem size, software-based aligners can take multiple CPU-days to process the sequence data, creating a bottleneck point in bioinformatic analysis flow. Reconfigurable accelerator can achieve high performance for such computation by providing massive parallelism, but at the expense of programming...
The traditional ortho-rectification technique for remotely sensed imagery, which is performed on the basis of ground image processing platform, has been unable to meet the timeliness requirements. To solve this problem, this paper presents the research on ortho-rectification technique based on field programmable gate array (FPGA) platform, which can be implemented onboard and spaceborne for a real-time...
Rapid and low power computation of optical flow (OF) is potentially useful in robotics. The dynamic vision sensor (DVS) event camera produces quick and sparse output, and has high dynamic range, but conventional OF algorithms are frame-based and cannot be directly used with event-based cameras. Previous DVS OF methods do not work well with dense textured input and are designed for implementation in...
As the first NP-complete problem, the Boolean satisfiability (SAT) problem is the key problem in computer theory and application. FPGA has been address frequently to accelerate the SAT solving process in the last few years, owing to its parallelism and flexibility. In this paper, we have proposed a novel SAT solver adopting an improved local search algorithm on the reconfigurable hardware platform...
Modular polynomial multiplication is the most computationally intensive operation in many homomorphic encryption schemes. In order to accelerate homomorphic computations, we propose a software/hardware (SW/HW) co-designed accelerator integrating fast software algorithms with a configurable hardware polynomial multiplier. The hardware accelerator is implemented through a High-Level Synthesis (HLS)...
Reducing the noise content in an image is the important factor in image processing and its applications. Some of the noises which cause a serious degradation in the image quality are multiplicative noise, salt and pepper noise, impulse noise, gaussian noise, additive noise etc. Among these, salt and pepper noise can be eliminated using median filtering techniques. Sorting techniques have been beneficial...
The maximum Lyapunov exponent (MLE) of a dynamic system is a quantity that characterizes the degree of separation of two infinitesimally close paths, it gives a measure of the average rate of exponential divergence of nearby orbits. It is known as a general indicator of the presence of chaos in a dynamic system. This quantifier has been applied in diverse fields, such as biomedicine and finance, in...
In this paper, image processing algorithms designed in Zynq SoC using the Vivado HLS tool are presented and compared with hand-coded designs. In Vivado HLS, the designer has the opportunity to employ libraries similar to OpenCV, a library that is well-known and wide used by software designers. The algorithms are compared in terms of area resources in two conditions: using the libraries and not using...
SAT is one of the most important basic problems of many areas of computer science and control science. SAT solvers are software or hardware to solve an SAT instance. In this paper, an instance-specified SAT solver was developed with FPGA, which implements the DPLL algorithm with our innovative random variable selection. Moreover, we also introduced an innovative tool-chain of our SAT solver, which...
We present a dataflow based performance estimation and synthesis framework that will help hardware designers quantify the algorithm performance and synthesize their HW designs onto Field Programmable Gate Arrays (FPGAs). Typically, Digital Signal Processing (DSP) systems are designed by making gradual architectural choices in HW refinement steps. These decisions are based on performance quantification...
The biometric encryption system is a significant addition in the areas of privacy, security and convenience among its users. The intent of this research is to propose an RSA based biometric encryption system which can be realized on field programmable gate arrays (FPGAs) using hardware-software co-design methods. Due to the high number of hackers that stand to profit from sub-par security methods,...
In this work, we share our experience in using High-Level Synthesis (HLS) for rapid development of an optical flow design on FPGA. We have performed HLS using Vivado HLS as well as a HLS tool we have developed for the optical flow design at hand and similar video processing problems. The paper first describes the design problem we have and then discusses our own HLS tool. The tool we developed has...
Intra prediction algorithm in the recently developed High Efficiency Video Coding (HEVC) standard has very high computational complexity. High-level synthesis (HLS) tools are started to be successfully used for FPGA implementations of digital signal processing algorithms. Therefore, in this paper, the first FPGA implementation of HEVC intra prediction algorithm using a HLS tool in the literature is...
Adaptive radiotherapy is a technique intended to increase the accuracy of radiotherapy. Currently, it is not clinically feasible due to the time required to process the images of patient anatomy. Hardware acceleration of image processing algorithms may allow them to be carried out in a clinically acceptable timeframe. This paper presents the experiences encountered using high-level synthesis tools...
Stereo matching is a crucial step for acquiring depth information from stereo images. However, it is still challenging to achieve good performance in both speed and accuracy for various stereo vision applications. In this paper, a hardware-compatible stereo matching algorithm is proposed; its associated hardware implementation is also presented. The proposed algorithm can produce high-quality disparity...
One of the major problems in communication is the secure transportation of data over communication protocols. This paper presents a feasible resolution for Rijindael's encryption and decryption using VHDL for FPGA (cyclone III) & ‘C’ running over Nios II processor. The Nios II is a versatile embedded processor which is high performance, of lower cost and power consumption, has low complexity combining...
One of the major problems in communication is the secure transportation of data over communication protocols. This paper presents a feasible resolution for Rijindael's encryption and decryption using VHDL for FPGA (cyclone III) & ‘C’ running over Nios II processor. The Nios II is a versatile embedded processor which is high performance, of lower cost and power consumption, has low complexity combining...
Sorting represents one of the most important operations in data center applications. In this paper, we propose a hardware-software FPGA accelerated based solution for very large data set merge sorting. The accelerator is using a FIFO based approach for sorting. The main contributions of the proposed solution are: (i) configurable FIFO buffers in order to address the variable size of the pre-sorted...
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