The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
Cooperation of software and hardware with hybrid architectures, such as Xilinx Zynq SoC combining ARM CPU and FPGA fabric, is a high-performance and low-power platform for accelerating RSA Algorithm. This paper adopts the none-subtraction Montgomery algorithm and the Chinese Remainder Theorem (CRT) to implement high-speed RSA processors, and deploys a 48-node cluster infrastructure based on Zynq SoC...
The detection and matching of point features play an important role in most of the computer vision algorithms, such as; for 3-D reconstruction and robotics navigation, localization and mapping. Over the last years various detectors and descriptors have been proposed and successfully applied to the different applications. However, the developed detectors are based on computationally intensive algorithms,...
Routing of nets is one of the most time-consuming steps in the FPGA design flow. While existing works have described ways of accelerating the process through parallelization, they are not scalable. In this paper, we propose ParaFRo, a two-phase hybrid parallel FPGA router using fine-grained synchronization and partitioning. The first phase of the router aims to exploit the maximum parallelism available...
MIMO system is widely studied for its high performance in wireless communication, of which the THP algorithm is a bottleneck of performance. Generally the THP is implemented in ASIC for high performance, which unfortunately makes it a difficulty for system updating. Compared to the ASIC solution, configurable processing, as its inherent flexibility and extension, becomes a promising solution for this...
The Fast Fourier Transform (FFT) is a widely used algorithm for spectral analysis of signals and is widely used in applications of communications, biomedical signal processing, industrial process control, etc. Its wide usage and application has resulted in the implementation of a number of FFT algorithms for inputs of various sizes, dimensions, and platform types such as desktop computers, graphic...
Real-time processing is one aspect of the Big Data situation, and it requires an unconventional approach to solve the recent problems that appear at both software and hardware levels. The continuous increase of data velocity has placed a tremendous pressure on the existing systems, and the current volumes of Big Data limit the efforts of storing everything at a pre-processing stage. Hence, on-the-fly...
Currently, many consumer game machines are based on the operations of processors. However, in the field programmable gate array (FPGA) research field, various FPGA game solvers have been developed recently. The processing speeds of such FPGA game solvers can reach about 1000 times faster than processor-based operations. This paper explains the development of one such FPGA game solvers, the Blokus...
The skyline query operation (also called the “maximum vector problem”) is used to identify potentially interesting or useful data points in large sets of multi-dimensional data. When the data change over time (through addition and subtraction of points), this is called the “continuous skyline” query. The 2015 MEMOCODE Design Contest problem is to implement a system to efficiently compute the continuous...
FPGA-based soft processors customized for operations on sparse graphs can deliver significant performance improvements over conventional organizations (ARMv7 CPUs) for bulk synchronous sparse graph algorithms. We develop a stripped-down soft processor ISA to implement specific repetitive operations on graph nodes and edges that are commonly observed in sparse graph computations. In the processing...
Implementing applications on Reconfigurable Computing Architectures (RCAs) is an important research topic because of their high potential to accelerate a wide range of functions. Nevertheless, configuring and programming RCAs is a long-standing challenge. In this paper, we propose a design methodology to map an algorithm on an FPGA preconfigured with a Coarse-Grained Reconfigurable Architecture (CGRA)...
The spatio-temporal synthesis of parallel structure of transformation matrix of 8-point algorithm of reverse fast cosine transformation with application of spatio-temporal graphs is offered. The comparative analysis of the known developments of the specialized processors of reverse fast cosine transformation is conducted. At practical realization of the specialized processor RFCT and its synthesis...
Using low-power symmetric multi-cores on FPGAs are becoming ubiquitous in embedded computing. This is due to the emergence of power and energy as key design metrics, as important as performance. This leads to the requirement of powerful and reliable tools, which will be used for the Design Space Exploration (DSE) based on power and energy at an early stage of the design flow. In this paper, we propose...
Fast Fourier Transform (FFT) is one of the fundamental operations in digital signal processing area. Splitradix Fast Fourier Transform (SRFFT) approximates the minimum number of multiplications by theory among all the FFT algorithms, therefore SRFFT is a good candidate for the implementation of a low power FFT processor. In this PhD work, we aim to implement a novel low power Split-Radix FFT processor...
Harnessing the full capabilities offered by reconfigurable hardware is still a demanding task: the lack of proper methodologies and the intrinsic time consuming and error prone tailoring of these systems around the specific application places a barrier to the adoption of this technology. Partial and Dynamic Reconfiguration (PDR), in this context, is a specific feature whose potential is undiscussed...
The continuous strive for improvements in visual realism is progressively increasing the complexity of algorithms for simulating light physics to produce very realistic scenes. As a result, they are becoming more and more suitable for hardware acceleration, even if they introduce new challenges due to the high requirements in terms of resources. In this paper we propose a hardware implementation of...
In today's network-based cloud computing era, software applications are playing big role. The security of these software applications is paramount to the successful use of these applications. These applications utilize cryptographic algorithms to secure the data over the network through encryption and decryption processes. The use of parallel processors is now common in both mobile and cloud computing...
Increasing the number of processors in a single chip toward network-based many-core systems requires a run-time task allocation algorithm. We propose an efficient mapping algorithm that assigns communicating tasks of incoming applications onto resources of a many-core system utilizing Network-on-Chip paradigm. In our contiguous neighborhood allocation (CoNA) algorithm, we target at the reduction of...
Reconfigurable hardware can be used as an energy and performance efficient co-processing solution to accelerate certain types of applications. To facilitate the design of hardware accelerators we have proposed a methodology that adopts the stream-based computing model and the usage of Graphics Processing Units as prototyping platforms. In this paper we go a step further and propose a new modular architecture...
Recently, much research has been conducted for security of data transactions on embedded platforms. Advanced Encryption Standard (AES) is considered as one of a candidate algorithm for data encryption/decryption. One important application of this standard is cryptography on smart cards. In this paper we describe a 32-bits architecture developed for Rijndael algorithm to accelerate execution on 32-bits...
The development of industrial control and measurement systems is often based on modular commercial off the-shelf hardware. Lately, for these platforms reconfigurable I/O modules with field-programmable gate arrays (FPGA) have gained significance, since they allow the implementation of data processing functionality very close to the data acquisition interfaces. However, algorithm complexity and floating-point...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.