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Financial exchanges provide real time data feeds containing trade, order and status information to brokers, traders and other market makers. ITCH is one such market data feed that is disseminated by the NASDAQ exchange. The work presented in this paper describes an FPGA based ITCH feed handler and processing system. The handler, built on the Stone Ridge RDX-11 hardware platform with a combination...
Montgomery modular multiplication is one of the fundamental operations used in cryptographic algorithms, such as RSA and Elliptic Curve Cryptosystems. At CHES 1999, Tenca and Koç proposed the Multiple-Word Radix-2 Montgomery Multiplication (MWR2MM) algorithm and introduced a now-classic architecture for implementing Montgomery multiplication in hardware. With parameters optimized for minimum latency,...
The design flow of Fast Fourier Transform devices development using the method of algorithmic operation devices synthesis from graphical representation of algorithms is proposed. Their automatic synthesis for various numbers of input data with different word length and their comparative evaluation are performed.
In today's world there is a growing demand for real-time implementation of cryptographic algorithms which are being used in secure communication systems, networks and security systems. Traditional computing techniques involved the use of application specific integrated circuits to achieve high performance but with extremely inflexible hardware design meanwhile the flexibility of hardware design was...
This work presents a high-level synthesis methodology that uses the abstract state machines (ASMs) formalism as an intermediate representation (IR). We perform scheduling and allocation on this IR, and generate synthesizable VHDL. We have the following advantages when using ASMs as an IR: 1) it allows the specification of both sequential and parallel computation, 2) it supports an extension of a clean...
The paper is dedicated to hardware accelerators for data sorting using tree-based recursive algorithms. Since recursive calls are not directly supported by hardware description languages, they are implemented using the model of a hierarchical finite state machine. The paper presents new results in: 1) computational models and hardware architectures; 2) optimization and parallel execution of recursive...
In order to save the hardware cost and reduce the power consuming in Reed-Solomon codec, a reconfigurable multi-mode codec is presented, which provides support to encoder and decoder. The reconfigurable calculation module (RCM) in the codec can be reconfigured to perform as a linear feedback shift register (LFSR), syndrome generator and Chien's search algorithm calculator and can handle variable error...
The paper describes the hardware implementation and optimization of recursive algorithms that sort data using binary trees. Since recursive calls are not directly supported by hardware description languages, they are implemented using the known model of a hierarchical finite state machine (HFSM). The paper suggests new hardware-oriented recursive algorithms, describes their implementation in hardware;...
The paper describes the hardware implementation and optimization of parallel recursive algorithms that sort data using binary trees. Since recursive calls are not directly supported by hardware description languages, they are implemented using the model of a hierarchical finite state machine (HFSM). Parallel processing is achieved by constructing N binary trees (N>;1) and applying concurrent sorting...
This paper designs a reconfigurable video MTD IP core, which established in XUP Virtex-II Pro development system platform. The design takes System Generator for the development tool, which is a system-level modeling tool developed by Xilinx Inc, to built a reconfigurable video MTD algorithm in MATLAB/Simulink environment, which is available for the FPGA platform. Then the algorithm is solidified as...
Finding an optimum function is not only a theoretical mathematical problem but also a particular engineering problem. Many aspects in the electrical and electronics field (by example: image processing, filter matching, optimization of network parameters, resources allocation) can be solved by finding a target function and his minimum or maximum. For such problems, usually an analytical solution is...
This paper present the design and analysis of 8-bit Smith Waterman (SW) based DNA sequence alignment accelerator's core on ASIC design flow. The objective of the project is to construct and analyse the core module that can perform the Smith Waterman algorithm's operations, which are comparing, scoring and back tracing, using the technique used in on ASIC design flow. Nowadays, the DNA and protein...
This paper presents the design and analysis high performance matrix filling for DNA sequence alignment accelerator using ASIC design flow. The objective of this paper is to design and analysis matrix module of DNA sequence alignment accelerator using clock cycle to get high performance. The scope of this paper is to optimize the DNA sequences alignment on the matrix filling module by implementing...
Advanced Encryption Standard, a federal information processing standard is an approved cryptographic algorithm that can be used to protect electronic data. The AES can be programmed in software or built with pure hardware. However field programmable gate array offers a quicker and more customizable solution. This paper presents the AES algorithm with regard to FPGA and the very high speed integrated...
FSM-based and microcode-based controllers are two widely known techniques used for memory built-in self test (MBIST). FSM-based controller is commonly the hardwired BIST whilst microcode-based controller is a programmable memory BIST (P-MBIST) controller. The P-MBIST is popular because of their flexibility of programming new test algorithms. Recently, the FSM-based memory BIST has evolved from hardwired...
Median filter has good capabilities for reducing a variety kind of random noise, and causes less ambiguity than linear smoothing filters under same processing size. In order to suppress the impulse noise of digital video signal and meet the system's needs of real-time, it is of great significance to do fast filtering of image based on hardware. By analyzing the common 3×3 filtering window's mathematical...
This work presents the hardware implementation of four hardware profile stream ciphers from the eSTREAM project. The hardware architectures are implemented using structural VHDL and, taking into account the simulation results, the best algorithm for hardware implementation is Trivium, with an 80-bit security level. This implementation requires 8 ALUTs, 289 registers, has a maximum frequency of 915...
In this article, a FPGA implementation of the Maximal Matching with Round-Robin Selection (MMRRS) scheduling algorithm for Virtual Output Queuing (VOQ) switches is presented. Implementation is done in the VERILOG hardware description language. The results results obtained from the software model simulation and hardware implementation in XILINX Virtex 5 proved that the implementation is correct. The...
Due the computational complexity of video processing algorithms the practical implementation of modern video encoders, like H.264/SVC, normally demands for some kind of hardware acceleration. In this paper we present a new integrated computational hardware module, able to perform the H.264 encoder algorithms of Discrete Cosine Transform, Hadamard Transform and Quantization. All these hardware modules...
Many hardware efficient algorithms exists for hardware signal processing architecture. Among these algorithm is a set of shift-add algorithms collectively known as CORDIC (Coordinate Rotation for Digital Computers) for computing a wide range of functions including certain trigonometric, hyperbolic, linear and logarithmic functions. The paper compares the different CORDIC architectures with respect...
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