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The aim of this paper is to design multiplier circuits for artificial neural network applications. The efficient use of area and speed performance has become a challenging task VLSI design field. In this works, radix-4 booth multiplier and radix-2 booth multiplier algorithms are analyzed based on its area used and speed performance. The less area used means the multiplier is more efficient in usage...
In order to solve the question for the 32-bit multiplier to do a variety of bit-length multiplication fast in the form of reusing resource on the FPGA, radix-4 booth modified algorithm is studied, and a bit-length controller is designed to control some bits, partial product generator and fast adder's structure are improved, so as to reuse most of the hardware resource in 8-bit or 16-bit multiplication...
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