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We present a practical, systematical method for the evaluation of the soft error rate (SER) of microelectronic devices. Existing methodologies, practices and tools are integrated in a common approach while highlighting the need for specific data or tools. The showcased method is particularly adapted for evaluating the SER of very complex microelectronic devices by engineers confronted to increasingly...
This paper presents a self-testing framework targeting the LEON3 embedded microprocessor with built-in test-scheduling features. The proposed design exploits existing post production test sets, designed for software-based testing of embedded microprocessors. The framework also includes a constraint-based approach of test-routine scheduling. The initial results show that the test execution time could...
Performance evaluation techniques for fundamental graphics algorithms and for algorithms to be used in multimedia and embedded systems are investigated. Models of computation considering only arithmetic and logic operations taken on input data are regarded as inadequate for processors with instruction-level parallelism. For experimental evaluation of graphics algorithms clock-cycle counting is found...
In this paper, we present a new technique to improve the reliability of H-tree SRAM memories. This technique deals with the SRAM power-bus monitoring by using built-in current sensor (BICS) circuits that detect abnormal current dissipation in the memory power-bus. This abnormal current is the result of a single-event upset (SEU) in the memory and it is generated during the inversion of the state of...
The challenges of deriving early-adopter competitive advantage, even with fabless access to process technology, through leveraging features offered by the advanced, and possibly disruptive, process technologies in real SoC products, are outlined. A structured methodology for addressing these challenges, and bridging the gap between process and design, sufficiently early in the development cycle to...
To increase memory bandwidth with minimum area overhead, the new concept of 3D-stacked memory structure consisting of a small sense amplifier shared with a few 3D memory cells has been presented. The 16 bit 3D-stacked TiO2 memory chip was fabricated and demonstrated. The estimated bandwidth per unit area of 3D-stacked memory in sub-65 nm CMOS technology indicates that the 3D-stacked memory has potential...
Multi-core SoC created great opportunities to increase overall system performance while keeping the power in check but also created many design challenges that designers must now overcome. The challenge of doubling performance every two years used to drive superscalar design with more functional units running concurrently or deeper pipeline racing for highest frequency at the cost of higher power...
This paper describes a methodology for building a reliable internet core router that considers the vulnerability of its electronic components to single event upset (SEU). It begins with a set of meaningful system level metrics that can be related to product reliability requirements. A specification is then defined that can be effectively used during the system architecture, silicon and software design...
The imaging laser radar is fine measure equipment for TAN with the ability to get the high precision 3D terrain. A 3D terrain matching processor was needed to be designed for the specifical application. In this paper, base on the specialty of the imaging laser radar, the3D terrain matching processor was designed, with scheme of DSP+FPGA calculating engine, multi-level memory system, flexible parallel...
Worst case execution time analysis based on measurements requires large test suites to obtain reliable numbers. We are thus developing tools to efficiently generate these test sets in a whitebox-testing approach. To make project progress measurable and guard against regressions, a benchmarking suite is sought for. We present a set of requirements that have been collected and outline the design of...
In 2006, John Mellor-Crummey and Michael Scott received the Dijkstra Prize in distributed computing for their 1991 paper on algorithms for scalable synchronization on shared memory multiprocessors, which included a novel spin-lock algorithm (a.k.a. MCS spin-lock) that carefully distributes spin locations in memory to lessen the impact of bandwidth limitations on spin algorithms. Their empirical work...
The ever changing demands on computational resources has information systems managers looking for solutions that are more flexible. Using a ldquobigger boxrdquo that has more and faster processors and permanent storage or more random access memory (RAM) is not a viable solution as the system usage patterns vary. In order for a system to handle the peak load adequately, it will go underutilized much...
Fast Fourier Transform (FFT) is the most basic and essential part of Software Defined Radio (SDR). Therefore, designing regular, reconfigurable, modular and low hardware complexity FFT computation block is very important. A single FFT block should be configurable for varying length FFT computation and also for computation of different transforms like DCT, DST etc. In this paper, the authors analyze...
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