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This paper describes two examples of nano-packaging technology using surface activated bonding (SAB): vertical contact of CNTs via to metal substrate, and heterogeneous bonding such as Si-Si3N4 and Si-Al2O3 wafers. In the both cases, controlled layer in nanometer-scale of the interface is essential in achieving the desired characteristics of the bonded interface‥
Process scaling is well know to increase overall chip-level soft error rates (SER) if no additional mitigation techniques are applied [Seifert04]. The purpose of this study is to summarize recent investigations conducted by the author to characterize the SER benefits and limitations of one particular SER mitigation technique: radiation hardened sequentials that utilize local redundancy. The studied...
This paper reviews recent experimental confirmations that the intrinsic radiation robustness of commercial CMOS technologies naturally improves with the down-scaling. When additionally using innovative design techniques, it becomes now possible to assure that performance and radiation-hardness are both met. An illustration is given with an original nano-power and radiation-hardened 8 Mb SRAM designed...
The power consumption and the matching will be the principal issues at the 32 nm node and below. In this context, Ultra-Thin Body devices are extensively studied for the end-of-roadmap CMOS. In this paper we present the SON technology, leading to the simple fabrication of sustained mono-Si nano-membranes over an empty tunnel, and discuss on the application of this process to build-up electronic devices...
To increase memory bandwidth with minimum area overhead, the new concept of 3D-stacked memory structure consisting of a small sense amplifier shared with a few 3D memory cells has been presented. The 16 bit 3D-stacked TiO2 memory chip was fabricated and demonstrated. The estimated bandwidth per unit area of 3D-stacked memory in sub-65 nm CMOS technology indicates that the 3D-stacked memory has potential...
Novel 3D stacked gate-all-around multichannel CMOS architectures were developed to propose low leakage solutions and new design opportunities for sub-32 nm nodes. Those architectures offer specific advantages compared to other planar or non planar CMOS devices. In particular, ultra-low IOFF (< 20 pA/mum) and high ION (> 2.2 mA/mum) were demonstrated. Moreover, those transistors do not suffer...
ldquoDevelopment for advanced thermoelectric conversion systemsrdquo supported by the new energy and industrial technology development organization (NEDO) has been successfully completed as one of the Japanese national energy conservation projects. Three types of the cascaded thermoelectric modules operating up to 850 K in high electrode temperature and two types of Bi-Te thermoelectric modules operating...
The polycrystalline samples of BaSi2, SrSi2, and LaSi were prepared by spark plasma sintering (SPS). The electrical resistivity (rho) and Seebeck coefficient (S) were measured above room temperature. The S of BaSi2 was negative and the absolute values were rather high (-669 muVK-1 at 337 K). The S of SrSi2 was positive and the absolute values were lower (118 muVK-1 at 332 K) than those of BaSi2. For...
Bulk nanostructured (Bi,Sb)2Te3 compounds and GeTe based amorphous/nanocrystal composites have been successfully fabricated by the combined hydrothermal/hot-pressing and quenching/annealing methods, respectively. The (Bi,Sb)2Te3 nanopowders synthesized by hydrothermal method exhibit a hollow-like structure. After hot-pressing, the nanoscale grains varying from tens to hundreds of nanometers were found...
In this study, we fabricated in-plane thermoelectric micro-generators (4 mm times 4 mm) based on bismuth telluride thin films by using flash evaporation method. The thermoelectric properties of as-grown thin films are lower than those of bulk materials. Therefore the as-grown thin films were annealed in hydrogen at atmospheric pressure for 1 hour in a temperature range of 200 degC. to 400degC. By...
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