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AXIe is a new standard for test and measurement. It provides an open, high-performance platform for instrument module. In order to reduce the complexity of developing AXIe instrument module, the authors designed an interface component by taking a FPGA as core controller. The component implements an AXIe interface and two High Speed Mezzanine Card (HSMC) interfaces which are used to connect different...
The work developed has as basis the networks/protocols described in the standard IEC 62439-3 Industrial automation networks - High availability automation networks: PRP and HSR. The similarities of both networks and a software implementation over Linux of PRP protocol have been the starting points taken for this work. A prototype of a HSR node has been developed; this prototype was proved over some...
FPGA-CF is an open-source, portable, extensible communications package that consists of a small hardware core (less than 600 slices) and and a host-software library/API. It enables a host PC to transmit data at 120 Mb/s to Xilinx-based FPGA boards via Ethernet using standard internet protocols. The hardware core is directly connected to the Xilinx internal configuration port (ICAP) and supports all...
This paper describes a design of network remote control based on Ethernet controller RTL8019AS and FPGA chip EP3C25Q240C8N. It's through the Altera NIOS II soft-core processor and a simplified TCP/IP protocol LWIP to complete the Ethernet Communication Protocol, and FPGA can configure and control RTL8019AS. Then the information can be communication between FPGA and PC, in order to achieve network...
We report on a Synchronous Ethernet based clock distribution and timestamp synchronization implementation over 1000BASE-T (Gigabit over twisted pair) Ethernet. A central 125 MHz global clock is distributed to all detector modules using only commercial off-the-shelf components. The timestamps generated on different modules has a maximum fixed offset of 24-60 ns (depending on the switch tested), and...
This paper presents a research and design method of plug-type IP information monitoring equipment based on parallel algorithm. It mainly uses the Ethernet hub and field-programmable gate array (FPGA) technology to implement the detection and management of full-duplex IP datagram. Meanwhile using time interval as a judge to analyze and process IP datagram. By detecting, the device can meet the design...
This paper describes a Field Programmable Gate Array hardware based Deep Packet Inspection Engine that uses regular expression matchers to simultaneously categorize and look for malicious signatures in Ethernet packets. This was a submission to the 2010 MEMOCODE Design Contest. It is the fastest Xilinx FPGA based design with a throughput of 734 Mbit/sec and the 2nd fastest overall, out of all designs...
MEMOCODE Design Contest challenged teams to implement the architecture for a unique type of Deep Packet Inspector called CANSCID. This paper describes this unique problem statement, and the motivation for choosing it. This paper is followed by short descriptions prepared by individual teams detailing their particular approach to solving the problem.
As FPGAs become larger and more powerful, they are increasingly used as accelerator devices for compute-intensive functions. Input/Output (I/O) speeds can become a bottleneck and directly affect the performance of a reconfigurable accelerator since the chip will idle when there are no data available. While PCI Express represents the currently fastest and most expensive solution to connect a FPGA to...
The PROFINET IEC 61158 standardized Real Time Ethernet (RTE) protocol, Class C, has traditionally been limited by an artificially imposed 250us cycle time, originating from the requirement to ensure that full-sized legacy Ethernet frames can be transmitted in a single cycle through a network. Occasionally, especially in the case of high performance motion-control systems, this minimum cycle time is...
This paper introduces a SOPC high-speed interconnection platform based on FPGA convenient for integrate processing system with Ethernet. Embedded processor PowerPC405e, corporated with logic array, implement seamless connection with processing system, as well as gigabit Ethernet. It shows flexibility and efficiency through data storage and playback with NAS storage system.
Ethernet based network protocol replaces fieldbus systems due to its high speed, safety, and extendibility. At the system level, use of an additional network requires effort to implement the new environment. The user has to analyze and organize two networks. This paper proposes FPGA based network controller between Ethernet and EtherCAT. It does not incur additional cost and effort. As it is based...
As real-time industrial control systems scale up, single real-time local area network (LAN) is no longer sufficient; instead, we need real-time switches to merge many real-time LANs into real-time wide area networks (WANs). However, nowadays commercially-off-the-shelf WAN switches are designed for best-effort Internet traffic rather than real-time traffic. To address this problem, we propose a real-time...
Recent trends show an increasing number of weblabs, implemented at universities and schools, supporting practical training in technical courses and providing the ability to remotely conduct experiments. However, their implementation is typically based on individual architectures, unable of being reconfigured with different instruments/modules usually required by every experiment. In this paper, we...
We present a dynamic computing platform that allows for rapid prototyping of image and video processing applications systems. Here, an Ethernet MAC is used to stream video in and out of the FPGA. The output video is also sent to a video port for display. The system features a simple way to specify the dynamic video processing modules that are going to be multiplexed in time. The dynamic control is...
Network fragmentation is the process of splitting a large amount of communication data into smaller fragments that comply with the Maximum Transmission Unit supported by the interconnect. We present a novel fragmentation approach which optimises communication fragmentation based on the amount of data remaining to be exchanged. Our fragmentation approach has up to 30% lower latency when exchanging...
We report on a distributed online coincidence detection implementation that we have recently added to the miniPET-II small animal PET scanner. The implementation uses standard Ethernet and IP multicasting techniques, therefore no architectural changes were necessary to the existing system. For 2D reconstruction the implementation scales with the number of detectors in the system, so it can be used...
Web service is a common Internet application that enables interactions of machines over a network. As to establish ubiquitous Internet, enabling Web services on embedded systems is certainly among the development trend in near future. This paper presents an implementation of REST style or RESTful Web services on embedded system. The prototype had been implemented using a Xilinx Spartan-3E Starter...
Parallel architecture has been used for packet processing of high speed links. Essential to such architecture is a load balancer which responsible for packet dispatching. In this paper, we design an embedded system for high speed OC192 network traffic load balancing. In the system, incoming traffic is load-balanced to 12 processing engines through Ethernet. In order to reasonably dispatch traffic...
The communication manager module embedded in a dedicated system configurable via Internet design description and XILINX Spartan 3 FPGA implementation are presented. Keeping Internet connectivity as a priority, minimum subsets of IEEE 802.3 standard rules for Ethernet data interchange and RFC826 and RFC791 recommendations for address resolution protocol (ARP) and Internet protocol (IP) respectively,...
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