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In nanometer technologies, circuits are more and more sensitive to various kinds of perturbations. Alpha particles and atmospheric neutrons are affecting storage elements as well as the combinational logic. In the past, the major efforts were related on memories. However, as the whole situation is getting worse, solutions that protect the entire design are mandatory. Solutions for detecting the error...
This paper presents a new algorithm for the correction of single residue digit error in Redundant Residue Number System. The location and magnitude of error can be extracted directly from a minimum size lookup table. This is made possible by the introduction of a new syndrome, which is proven to be unique for every different residue digit error with two criteria imposed on the choice of redundant...
This paper presents a design methodology for multiple bit error detection and correction in Galois field arithmetic circuits such as the bit parallel polynomial basis (PB) multipliers over GF(2m). These multipliers are crucial in most of the cryptographic hardware designs and hence it is essential to ensure that they are not vulnerable to security threats. Security threats arising from injected soft...
Soft errors in combinational logic have been considered as an important challenge for VLSI circuit design. As a kind of representative element of combinational logic, adders are widely used in arithmetic units. This paper presents a cost effective soft error mitigation technique for high speed parallel adders. By exploiting inherent hardware redundancy and temporal redundancy of circuit, this technique...
Modern many-core architectures with hundreds of cores provide a high computational potential. This makes them particularly interesting for scientific high-performance computing and simulation technology. Like all nano scaled semiconductor devices, many-core processors are prone to reliability harming factors like variations and soft errors. One way to improve the reliability of such systems is software-based...
Soft errors in combinational logic are becoming a serious problem for VLSI design. This paper presents an idle resources based SER reduction scheme for functional units of microprocessors. By exploiting unoccupied hardware and slack time in functional units, this technique reduces overheads of fault tolerance greatly. We combine C-element based error correction techniques with idle resources exploiting...
Recent studies have shown that an attacker can retrieve confidential information from cryptographic hardware (e.g. the secret key) by introducing internal faults. A secure and reliable implementation of cryptographic algorithms in hardware must be able to detect or correct such malicious attacks. Error detection/correction (EDC), through fault tolerance, could be an effective way to mitigate such...
Robust system design ensures that future systems continue to meet user expectations despite rising levels of underlying disturbances. This paper discusses two essential aspects of robust system design: 1. Effective post-silicon validation, despite staggering complexity of future systems, using a new technique called Instruction Footprint Recording and Analysis (IFRA). 2. Cost-effective design of systems...
This paper presents a new system architecture for implementing fault-tolerant information processing. The proposed structure relies on simple processing elements (PEs) arranged into a regular locally-interconnected array. Such an approach is a favorable way of implementing circuits with inherently unreliable nanodevices. Different network operations are achieved through binary programmable interconnections...
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