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In this paper we are going to study Array multiplier, Wallace multiplier, Bypassing multiplier, Modified Booth multiplier, Vedic multiplier and Booth recorded Wallace tree multiplier which have been proposed by different researchers. When the study of the various multipliers have been performed, Array multiplier is found to have the largest delay and large power consumption while Booth encoded Wallace...
In this paper, we present a performance comparison of Binary Coded Decimal (BCD) Adders on Field Programmable Gate Logic (FPGA) for functional and behavioural verification. Although it does not prove that the circuit is reversible, implementation on FPGA serves as a platform for functional verification of circuits. BCD adders are one such circuit which has gain wide research emphasis where BCD adders...
This paper portrays the selection of hardware unit architectures to be implemented in the new LNS based on a 32bit system. The implementations of the LNS multiply and divide only require a FXP adder, while the LNS addition and subtraction function comprised of several memories, FXP adders and multipliers together with other supporting logics. Thus, in choosing the best FXP adders and multipliers,...
Filtering being one of the most important modules in signal processing paradigm, this paper presents an FPGA implementation of various window-functions using CORDIC algorithm to minimize area-delay product. The existing window-architecture uses a linear CORDIC processor in series with circular CORDIC processor, that results in a long pipeline. Firstly, we replace the linear CORDIC with multiple optimized...
This paper presents a Reconfigurable Parallel Prefix Ling Adder. The proposed design can be partitioned to perform as one 16 bit, two 8 bit and four 4 bit adders. We also propose a new architecture for Enhanced Flagged Binary Adder (EFBA) designs which reduces the delay of operation considerably. The new adders are, therefore, modifications of conventional Reconfigurable Carry Lookahead Adder (CLA)...
This paper presents architecture of CORDIC, embedded with a scaling unit that has only minimal number of adders and shifters. It can be implemented in rotation mode as well as vectoring mode. The purpose of the design is to get a scaling free CORDIC unit preserving the design of original algorithm. The proposed design has a considerable reduction in hardware when compared with other scaling free architectures...
In this paper, parallel and digit-serial implementations of area-efficient 3-operand decimal adders are proposed. By using proposed analyzer circuits and the generation of correction terms with recursive schemes, our proposed decimal adders could perform efficient additions with three operands. Unit gate estimates and synthesis results show that our proposed adders are more area-efficient than those...
By introducing a signed-digit (SD) number arithmetic into a residue number system (RNS), arithmetic operations can be performed efficiently. In this paper, a high-speed modulo m SD addition algorithm is proposed, where m\in \{2^n-1, 2^n+1, 2^{2n}+1, 2^n\}. By using the modulo m SD adders, a modulo m SD multiplier can be implemented with a binary adder tree structure. We also present an algorithm for...
This work presents a synthesis framework that generates a formally verifiable RTL from a high level language. We develop an estimation model for area, delay and power metrics of arithmetic components for Xilinx Spartan 3 FPGA family. Our estimation model works 300 times faster than Xilinx's toolchain with an average error of 6.57\% for delay and 3.76\% for area estimations. Our framework extracts...
The 3N encoding process can simply add the input data N to its 1-bit left-shifted value 2N using the combinational digital circuits, such as ripple carry adder (RCA) or carry look-ahead adder (CLA). This paper presents an efficient algorithm and its hardware implementation. Results show that the proposed RCA-like 16-bit encoder achieves 25% less in hardware cost and 50% faster in speed performance...
Exploiting computational precision can improve performance significantly without losing accuracy in many applications. To enable this, we propose an innovative arithmetic logic unit (ALU) architecture that supports true dynamic precision operations on the fly. The proposed architecture targets both fixed-point and floating-point ALUs, but in this paper we focus mainly on the precision-controlling...
Decimal arithmetic has gained high impact on the overall performance of today's financial and commercial applications. Decimal additions and multiplication are the main decimal operations used in any decimal arithmetic algorithm. Decimal digit adders and decimal digit multipliers are usually the building blocks for higher order decimal adders and multipliers. FPGAs provide an efficient hardware platform...
This paper is primarily deals the construction of high speed adder circuit using Hardware Description Language (HDL) in the platform Xilinx ISE 9.2i and implement them on Field Programmable Gate Arrays (FPGAs) to analyze the design parameters. The motivation behind this investigation is that an adder is a very basic building block of Arithmetic Logic Unit (ALU) and would be a limiting factor in performance...
An efficient design of the reverse converter forthe three-moduli set {2n, 2n+1-1, 2n-1} is presented in thispaper. The reverse converter is structured by an adderbased on New Chinese Remainder Theorem II (NewCRT-II) conversion such that it can improve thehardware cost. The proposed conversion design iscompared with the existing works based on the standardCell TSMC 0.18µm CMOS technology. Under the...
The signal and image processing algorithm use multiplication as one of the basic arithmetic operation. So the efficient implementation of multiplier is always a challenge. The present work describes a method to build a faster array multiplier by delay optimized inter connection globally. The proposed array multiplier architecture performance in terms of delay and hardware is compared with conventional...
In this paper, we have proposed area-efficient 3-input decimal adders using simplified carry and sum vectors. By using proposed generator circuits and the recursive generation of correction terms, our proposed decimal adders could perform efficient summations with three inputs of operands. Synthesis shows that our proposed adders save up to 39.2 % area cost compared to previous reported decimal adders...
This paper presents a reconfigurable mechanism for the multiplier. The proposed mechanism is applied to generate a multiplier, whose data width, type and pipeline depth can be customized. The data width of each operand of these generated multipliers can be configured for 4i where i=1, 2, 3, 4, 5, 6, 7, 8. And the data type of operand can be unsigned or signed at will. The multiplier is composed of...
Effective exploitation of the application-specific parallel patterns and computation operations through their direct implementation in hardware is the base for construction of high-quality application-specific (re-)configurable application specific instruction set processors (ASIPs) and hardware accelerators for modern highly-demanding applications. Although it receives a lot of attention from the...
The need to have hardware support for decimal arithmetic is increasing in recent years because of the growth in the decimal data processing in commercial, financial and internet based applications. In this paper a new architecture for efficient Binary coded decimal (BCD) addition/subtraction is presented that can be reconfigured to perform binary addition/subtraction. The architecture is mainly designed,...
Synchronous hardware can be straight forwardly modelled as a function from input and (current) state to an updated state and output. The C?aSH compiler can translate such a transition function, described in a functional language, to synthesisable VHDL. Taking a hardware-oriented viewpoint, components can then be seen as an instantiation of such atransition function. An abstraction called Arrows is...
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