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This paper focuses on low complexity architectures for check node processing in Non-Binary LDPC decoders. To be specific, we focus on Extended Min-Sum decoders and consider the state-of-the-art Forward-Backward and Syndrome-Based approaches. We recall the presorting technique that allows for significant complexity reduction at the Elementary Check Node level. The Extended-Forward architecture is then...
Flash memories are gaining prominence for utilizing in large scale data centers (DCs) due to their high memory density, low power consumption and heat dissipation, and high access speed characteristics. The rate of degradation for a flash memory is largely affected by the amount and frequency of the erase/write operations, which is a challenge in the DC context that serves dynamically changing workloads...
This work proposes a systematic design approach to perform minimum and second minimum fast-searching in 2-dimensional xy-planes. This fast-searching approach can extremely improve the calculating timing in LDPC decoder architecture, especially for high row weights defined in IEEE 802.11n/ac/ax SPEC. In a design example with row weight of 22, our developed approach only requires about 42.9% of critical-path...
LDPC codes are deployed in many modern wired and wireless communication systems. While fully-parallel LDPC decoders are very efficient, they typically suffer from routing complexity. The Split-Row method effectively reduces this complexity with a minor performance loss. This paper shows the importance of symmetry in Split-Row architectures and proves that the implementation of Split-Row decoders based...
Lowering the power supply of a circuit can induce transient errors in the memory cells and timing errors in the computation units. In this paper, we consider the Taylor-Kuznetsov (TK) memory architecture with transient errors in the memory cells and with timing errors in the correction circuit. We provide a theoretical analysis of the performance of TK memories under transient errors and timing errors...
NHK (Japan Broadcasting Corporation) is conducting research on the next generation of digital terrestrial broadcasting system to enable large-volume content services such as UHDTV (ultra-high-definition television). In our previous study, we proposed spatially coupled low density parity check (SC-LDPC) codes for broadcasting. The lengths of these codes can be easily extended and are expected to have...
Polar codes are a new class of block codes with an explicit construction that provably achieve the capacity of various communications channels, even with the low-complexity successive-cancellation (SC) decoding algorithm. Yet, the more complex successive-cancellation list (SCL) decoding algorithm is gathering more attention lately as it significantly improves the error-correction performance of short-to...
Low-density parity check (LDPC) codes have been widely applied to many storage devices because of their good error correcting performance. However, power consumption and area cost are still the major issues for their hardware implementations. Therefore, power and area reduction techniques are necessary for the implementation of check node unit (CNU) of LDPC decoder. In this paper, a novel partially...
Multithreshold decoder (MTD) is the simplest type of majority decoder that decodes self-orthogonal codes. Low computational complexity and simple decoding hardware implementation of multithreshold decoders allow using them in high speed communication systems and data storage systems that require decoding information at speeds above 1 Gbit/s. A high-speed software binary multithreshold decoder using...
LDPC decoders on faulty hardware have received increasing attention over the last few years, mainly motivated by reliability issues in emerging nanotechnologies. As a main result, it was shown that LDPC decoders are naturally robust to hardware faults. LDPC encoders on faulty hardware have received less attention, and they are expected to be less robust to hardware faults. In this work, we propose...
This article presents a simple, less computational complexity method for constructing exponent matrix (3, K) having girth at least 8 of quasi-cyclic low-density parity-check (QC-LDPC) codes based on subtraction method. The construction of code deals with the generation of exponent matrix by three formulas. This method is flexible for any block-column length K. The simulations are shown in comparison...
Low Density Parity Check (LDPC) codes have been widely used in communications systems due to their high error correction capabilities. Recently these codes are also investigated for being exploited in high performance storage systems, especially when Non-Volatile Memory (NVM) technologies are used. The main drawback of using LDPC codes in storage systems with a high number of parallel channels is...
Soft decision decoding for Reed-Solomon codes has been proven to provide large coding gains in comparison to conventional hard decision decoding. Out of the numerous soft decoding algorithms, information set decoding has turned out to be an efficient approach, if coding gains larger than 0.5 dB are desired for the widely used RS(255,239) code. In this paper we investigate new hardware implementations...
A multi-mode QC-LDPC decoder is proposed to satisfy the 802.11n/ac WiFi standard. With code-specific design, the overall performance of the decoder is enhanced while ensuring an on-the-fly reconfigurable ability. The proposed architecture has been synthesized using an FPGA for measurements. A state-of-art error rate and implementation complexity are reported. Meanwhile, the throughput has been increased...
The computation of the Log-Likelihood Ratio (LLR) at the channel output may impose great demand of memory and hardware area, especially for high-order modulations. This paper introduces a new approach for the approximation of the LLR in AWGN channels based on the splitting of the original constellation into smaller sectors. Each new sector has a less complex configuration in which it is possible to...
We provide the first constructions of a new family of error-correcting codes called “energy-adaptive codes.” These codes are designed to enable adaptive circuit implementations that minimize the total system-level energy based on varying distances and target error probabilities. Recent work has explored fundamental limits and practical strategies for minimizing total (transmit + circuit) power, considering...
We propose without loss of generality strategies to achieve a high-throughput FPGA-based architecture for a binary Quasi-Cyclic Low-Density Parity-Check (QC-LDPC) code based on a circulant-1 identity matrix construction. We present a novel representation of the parity-check matrix (PCM) providing a multi-fold throughput gain. Splitting of the node processing algorithm enables us to achieve pipelining...
With scaling of process technologies and increase in process variations, embedded memories will be inherently unreliable. In this paper, we propose redundancy-free adaptive error-correcting codes for the noisy min-sum decoder subject to memory errors. We consider the popular memory error model with a binary symmetric channel. We first revisit the density evolution analysis proposed by Balatsoukas-Stimming...
Stochastic decoding can be applied to Low-Density Parity-Check codes in order to achieve high throughput with less area. However, most architectures suffer from large decoding latencies, due to the mechanism of stochastic computation. In this paper, three novel strategies, including the LUT-based initialization, the posterior-information-based hard decision and the Bit-Flipping-based post processing,...
As the reliability of NAND Flash memory keeps degrading, Low-Density Parity-Check (LDPC) codes are widely proposed to extend the endurance of Solid State Drive (SSD). However, implementing powerful decoding algorithm such as soft min-sum algorithm with high decoding speed comes along with higher hardware cost. To achieve efficient hardware cost, we propose a multi-strategy ECC scheme which consists...
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