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A continuous-time 5th order low-pass reconfigurable, highly linear, Gm-C filter exhibiting a tuning wide bandwidth is presented. The filter uses a new high-frequency, linear operational transconductance amplifier. The operational transconductance amplifier is based on two cross-coupling pairs with active source degeneration resistance that allows high linear, high frequency filter performance. A 5...
A 70-280 MHz 5th-order Chebyshev Gm-C low-pass filter was implemented in 0.13μm CMOS process to support both WiMedia UWB and lower rate IR-UWB applications. The filter response is accurately maintained over 4× frequency range by using unit Gm cell arrays and independent Q tuning circuit. To improve linearity of Gm-C filter in low supply voltage, a modified LC ladder topology...
An analog baseband chain for WiMedia MB-OFDM UWB and China UWB standard is presented. The baseband chain consists of a fifth-order chebyshev type low pass filter with two switchable cut-off frequencies. A programmable gain amplifier based on enhanced source degeneration architecture is also included. The chip was fabricated in TSMC 0.13-μ RF CMOS process. Measurement results show that the analog baseband...
This paper presents a 6th-order active-RC low-pass filter with 240 MHz to 500 MHz tunable bandwidth, which is suitable for the ultra-wideband transceivers. The filter consumes only 2.3 mA from 1.8 V supply voltage, which is mainly attributed to the proposed highly power-efficient operational amplifier (Opamp) with an adaptive-biased pole-cancellation push-pull source follower as the buffer stage to...
A third-order continuous-time delta-sigma modulator achieving 76dB dynamic range over 5MHz signal bandwidth is presented. The modulator has a monotonic lowpass signal transfer function and achieves over 70dB anti-aliasing. The prototype chip implemented in a 130nm CMOS process consumes 6mw power from a single 1.2V supply and occupies 0.56 mm2 active area.
This paper presents a response-translation technique to realize an ultra-low-cutoff lowpass filter in small area for biopotential acquisition systems. It is by exploiting a chopper-stabilized instrumentation amplifier (IA) with bandpass characteristic to obtain a lowpass response after chopper stabilization, resulting in substantial area savings because of relaxed time constant in the implementation...
A low power full custom Half-Band FIR digtal Alter with fixed coefficients used for sigma-delta ADC is presented. The Half-Band FIR digtal filter uses three- stage cascaded strcture and has linear phase and lowpass characteristics. It achieves passband ripple of 0.003dB and stopband attenuation of 82dB, and dissipates only 15mW with a 3V supply based on a 0.35um CMOS process.
To handle the 12dB peak-to-average-power ratio (PAPR) of OFDM signals in a 802.11a/g WLAN receiver baseband, an instantaneously companding system consisting of a 5-order low pass SC filter and a 10-bit pipeline ADC is presented. The filter cut-off and clock frequencies are 10MHz and 100MHz respectively and the ADC sampling frequency is 25MS/s. The filter provides the compressed output directly to...
Presented is a novel source-follower-based (SFB) bi-quad cell suitable for realizing continuous-time zero-pole type filters. Unlike the conventional SFB bi-quad cells that can only realize complex poles, additional complex zeros can be synthesized in the proposed one, by adding two feedforward capacitors. A 4th-order Chebyshev II fully differential low-pass filter prototype was fabricated in a 0.18-μm...
A weakly inverted MOS transconductor with wide input linear range and very low transconductance is proposed. The transconductor is achieved by efficient input voltage attenuation formed by connecting identical simple source coupled pairs in a scheme that provides very high extensibility of voltage scaling. Post-layout simulated results in a 0.35-μm standard CMOS process show that Gm in the range of...
This paper presents a design of a 3rd order Butterworth Gm-C Low Pass Filter (LPF) for WiMAX receivers in a 90 nm CMOS process. Due to its robustness to process parameter tolerances, a passive LC-ladder filter was emulated using the Signal Flow Graph (SFG) method. As a building block for the LPF, a highly linear operational transconductance amplifier (OTA) based on bias-offset cross-coupled differential...
In this study, square-root-domain (SRD) electronically-tunable first order transadmittance type that has voltage input and current output and transimpedance type that has current input and voltage output low-pass filters are proposed. Additionally transadmittance type first order multifunction filter that has low-pass, high-pass and all-pass outputs is realized. The transfer admittance parameter g...
We present the design of an ultra low power sixth-order Butterworth low pass GmC filter in 0.13 ??m CMOS process. A method to optimize the power consumption of a fully differential telescopic OTA is also presented to achieve an input linearity of 220 mVpp and transconductance value of 6 ??S. The OTA is then used to implement an ultra low power filter and to show the impact of parasitic capacitances...
This paper describes a high-dynamic-range 2.4 Hz-to-10 kHz wide-range tunable 5th-order Butterworth lowpass filter for biomedical applications. A differential gm-C topology in conjunction with a subthreshold-biased wide-gm-range OTA realizes efficiently a wide frequency tuning capability. For capacitance savings with consequent silicon area reduction, a merged use of floating real capacitor and grounded...
The design of a low-cutoff-frequency Gm-C low-pass filter is presented, the key part in the filter, the operational transconductance amplifier utilize a folded-cascode structure. As the circuit is desired to operate at low frequency, it is necessary to design a small linear trans-conductance amplifier employing a cross-coupled input stage. To compensate the gain loss, the auxiliary amplifiers are...
In this paper, a new current-mode second-order square-root-domain notch filter is proposed. The design is based on the state-space synthesis method with two subcircuit; square-root and squarer/divider circuits. In the circuit, the input and the output values, and dominant variables are all currents. Only MOS transistors and grounded capacitors are required to realize the filter circuit. Three cases...
The design of a second-order low-pass IIR filter based on time-mode signal processing circuits is presented. The filter is implemented using a set of building blocks that perform basic mathematical operations in the time-domain including time addition, weighted delayed time addition and subtraction, and unit delay. A second-order low-pass Chebyshev filter was designed in a 0.18 mum CMOS process. Simulation...
Compact passive LC ladder lowpass filters for pulse shaping are realized using a single inductor with multiple taps. Mutual coupling between different inductors in a ladder results in zeros on the real and imaginary axis and can cause an undershoot in the step response and reduced attenuation in the stopband. Techniques to mitigate these effects are described. A seventh order Bessel filter is realized...
A FLASH digital phase-locked loop (DPLL) is designed using 0.18 ??m CMOS process and a 3.3 V power supply. It operates in the frequency range 200 MHz - 2 GHz. The DPLL operation includes two stages: (1) a novel coarse-tuning stage based on a flash algorithm similar to the algorithm employed in flash A/D converters, and (2) a fine-tuning stage similar to conventional DPLLs. The flash portion of the...
This paper presents a full-CMOS single-chip Receiver PHY IC for VDSL2 systems. In the receiver part, the low-pass filter, VGA, and ADC is designed to have a wide dynamic range and gain control range because the signal from the VDSL2 line is variable depending on the distance. This chip is fabricated with 0.25 mum CMOS technology, and the die area is 5 mm times 5 mm. The power consumption is 250 mW...
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