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Interest in on-line error detection continues to grow as VLSI circuits increase in complexity. Concurrent checking is increasingly becoming a desirable characteristic thanks to its ability to detect transient faults that may occur in a circuit during normal operation. Accordingly, Concurrent Error Detection (CED) techniques allow the detection of transient faults, which probably not be detected in...
This paper presents a power and performance multi-objective Tabu Search based technique for designing application-specific Network-on-Chip architectures. The topology generation approach uses an automated technique to incorporate floorplan information and attain accurate values for wirelength and area. The method also takes dynamic effects such as contention into account, allowing performance constraints...
A Traffic-adaptive MAC protocol (TaMAC) for a Wireless Body Area Network (WBAN) is presented in this paper. The idle listening and overhearing problems are solved by exploiting the traffic information of the nodes. The protocol is supported by a traffic-based wakeup mechanism and a wakeup radio mechanism that are used to accommodate normal, emergency, and on-demand traffic in a reliable manner. Analytical...
In recent years various types of implantable medical devices have been proposed for monitoring various physiological parameters of human body. Long term maintenance-free operation of these devices requires extreme low-power operation to avoid periodic replacement of batteries. For real-time monitoring of health condition, the implantable medical devices also need to transmit the vital information...
There is a growing demand for high-performance, low-power systems, particularly in portable devices. New approaches to design are needed in technologies with feature sizes of 90 nm and below to reduce leakage power and to deal with process variations, which force designers to use increasingly conservative delay estimations. This paper presents a variable clock generator for a conventionally-designed...
This paper presents a Tabu search based approach for the topology synthesis of application-specific multicore architectures using an automated design technique. The Tabu search method incorporates multiple objectives in order to generate an optimal NoC topology which accounts for both power and performance factors. The method generates a system-level floorplan in each major stage of the topology synthesis...
A delay-locked loop (DLL)-based clock generator for dynamic frequency scaling has been developed in a 0.13um CMOS technology. The proposed clock generator can generate a wide-range of the multiplied clock signals ranging from 125MHz to 2GHz. In addition, thanks to the proposed anti-harmonic lock block, the clock generator can change the frequency dynamically in one cycle time of the reference clock...
The occurrence of errors are inevitable in modern VLSI technology and to overcome all possible errors is an expensive task. It not only consumes a lot of power but degrades the speed performance. By adopting an emerging concept in VLSI design and test-error-tolerance (ET), we managed to develop a novel error-tolerant adder which we named the Type II (ETAII). The circuit to some extent is able to ease...
In this paper we present a distributed supervisory strategy for load/frequency control problems in networked multi-area power systems. Coordination between the control center and the areas is accomplished via data networks subject to communication latency which is modelled by time-varying time-delay. The aim here is at finding strategies able of reconfiguring, whenever necessary in response to unexpected...
A delay-locked loop of multi-band selector with wide-locking range and low power dissipation is presented. The architecture of the proposed delay-locked loop consists of phase frequency detector, charge pump, band selector, multi-control delay line, and start-up circuit. The multi-band selector is used to extend operation frequency of delay-locked loop by switching the multi-control delay line. The...
This paper studies the impact of intra-die random variability on low-power digital circuit designs, specifically, circuit timing failures due to intra-die variability. We identify a new low-Vdd statistical failure mode that is strongly supply-voltage dependent and also introduce a simple yet novel method for quantifying the effects of process variability on digital timing - a delay overlapping stage...
This paper describes a design flow for the circuit-level optimization of a technology. The concurrent exploration of device characteristics and library design choices leads to a more application-optimal technology. We illustrate the design flow by: 1) analyzing the impact of buffer cell design, and 2) by optimizing a 130 nm technology for low operational power.
Class D amplifiers are becoming the most feasible solution for embedded audio application. However, distortions due to the non-linear nature of switching stage are the main drawback for this amplifier topology. This paper discusses the design and implementation of high fidelity audio class D using sliding mode control scheme. This design method proves to be a cost effective solution for industrial...
A 3.57-Gb/s, low-power, 2 31-1 output length, extended frequency range Pseudo Random Binary Sequence (PRBS) generator with an improved wave-pipeline technique is presented. The previous wave-pipeline technique bypasses the portion of feedback loop, and thereby relaxes the timing restriction of the critical path up to two shifting clock periods. While the generator operates at the 48% higher frequency...
This paper presents novel nonoverlapping cuspid-pulsed flip-flop, which consists of a cuspid-pulse generator and a domino-like latch. The cuspid-pulse generator supplies the domino-like latch with nonoverlapping negative and positive cuspid-shape pulses. The flip-flop allows the elimination of the second stage in the conventional semi-dynamic pulse-based flip-flops, leading to a significant reduction...
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