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“Safety margin” for a logic circuit introduces a performance overhead. But eliminating safety margin makes a system more prone to timing failure, particularly under dynamic operating variations. This paper presents dynamic timing control technique that allows a system to operate without any safety margin. The dynamic control method prevents timing errors utilizing time borrowing and elastic clocking...
This paper describes the realization of an interconnect Delay Insensitive (DI) FPGA architecture with distributed asynchronous control. This architecture maintains the basic block structure of traditional FPGAs allowing the potential use of existing FPGA design tools in block design. This asynchronous FPGA architecture is mainly aimed at tolerating the unpredictable delay variations caused by process...
A low power voltage management technique is proposed to reduce power consumption for domino circuits. Exploiting a rising and charge-sharing voltage allow the domino circuits to have both high performance and low power consumption. A test chip has been successfully validated to achieve 68% dynamic power consumption and 15% static power consumption respectively using TSMC 0.13um CMOS technology.
A novel energy efficient, Single Event Upset (SEU)/Single Event Transient (SET) tolerant Flip-Flop (FF) design is proposed which is suitable for ultra-low power systems that operate between sub-threshold (250mV) and super-threshold (1.0V) supply voltages. In comparison to an existing sense-amplifier based radhard FF, the proposed FF provides equivalent SEU/SET resilience at super-threshold voltage...
This paper introduces the first ever dynamic voltage scaling (DVS) technique for DRAM considering both the process skew and the operating frequency which is adopted for the consumer DDR2 SDRAM. The self-dynamic voltage scaling (SDVS) itself is a very powerful technique to stretch the battery life and increase the reliability of DRAM.
A multimedia applications processor is fabricated using a 28nm low-power process technology for ultra-low-power applications. Based on a 4-issue, 32 register version of the TMS320C64X+ VLIW DSP, this System on Chip (SoC) includes 32kB L1 and 128kB L2 caches, and I2S, SPI, UART, MultiMediaCard, and external memory interfaces (Fig. 7.5.1). The design incorporates over 600k instances of custom low-voltage...
Low power device design is now a vital field of research due to increase in demand of portable devices. This research paper proposes the modified Single Edge Triggered (SET) D-flip flop design for the portable applications. Design is tested for various substrate bias voltages in sub-threshold region to opt for better design. Design comparison between previously reported design and modified design...
Flip-flops (FF) typically consume more than 50% of random-logic power in an SoC chip, due to their redundant transition of internal nodes, when the input and the output are in the same state. Several low-power techniques have been proposed, but all of them incur transistor-count penalties, leading to an increase in size, which is too costly since flip-flops typically account for 50% of random-logic...
Increasing demand of portable devices creating larger scope in the field of Low power device design. VLSI designing of the efficient circuits is aiming towards the devices consuming less power and produces less delay with capability to operate in wider range of frequencies. This research paper proposes the modified Single Edge Triggered (SET) D-flip flop design for the low power applications. The...
Exploiting a charge sharing method enables a performance power management design for domino circuits. The domino circuits have both high performance and low power consumption. A test chip has been successfully validated using TSMC 0.13um CMOS technology. Reductions in dynamic power consumption of 68% and static power consumption of 15% are achieved.
A novel rotary clock network routing method is proposed for the low-power resonant rotary clocking technology which guarantees: 1. The balanced capacitive load driven by each of the tapping points on the rotary rings, 2. Customized bounded clock skew among all the registers on chip, 3. A sub-optimally minimized total wirelength of the clock wire routes. In the proposed method, a forest of steiner...
Multiple Supply Voltage (MSV) assignment has emerged as an appealing technique in low power IC design, due to its flexibility in balancing power and performance. However, clock skew scheduling, which has great impact on criticality of combinational paths in sequential circuit, has not been explored in the merit of MSV assignment. In this paper, we propose a discrete voltage assignment algorithm for...
Clock gating is an effective method of reducing power dissipation of a high-performance circuit. However, deployment of gated cells increases the difficulty of optimizing a clock tree. In this paper, we propose a delay-matching approach to addressing this problem. Delay-matching uses gated cells whose timing characteristics are similar to that of their clock buffer (inverter) counterparts. It attains...
Side channel attacks (SCAs) exploit the fact that security IC physical implementation of a cryptographic algorithm can leak information of the secret key. One of the most important SCA is Differential Power Analysis (DPA), that uses the power consumption dependence with the data processed to reveal critical information. To protect security devices against this issue, differential logic styles with...
Sometimes reducing the power dissipation of resource constrained electronic systems, such as those built for deep-space probes or for wearable devices is a top priority. In signal processing, it is possible to have an acceptable quality of the signal even introducing some errors. In this work, we analyze two methods to degrade the precision of arithmetic operations in DSP to save power. The first...
We propose a circuit technique for an 8T dual-port (DP) SRAM in order to screen degraded minimum operating voltage (Vmin) due to the write/read disturb issue. This circuitry allows us to generate the write/read disturb condition without relying on the conventional costly asynchronous operation. We designed and fabricated a 512-kb DP-SRAM macro using 28-nm low-power CMOS technology, and confirmed assured...
Clock networks contribute a significant fraction of dynamic power and can be a limiting factor in high-performance CPUs and SoCs. The need for multi-objective optimization over a large parameter space and the increasing impact of process variation make clock network synthesis particularly challenging. In this work, we develop new modeling techniques and algorithms, as well as a methodology, for clock...
Low-power devices are indispensable for modern electronic applications, and numerous hardware/software techniques have been developed for drastically reducing functional power dissipation. However, the testing of such low-power devices has increasingly become a serious problem, especially in at-speed scan testing where a transition is launched at the output of a flip-flop and the corresponding circuit...
The paper introduces a new low power, high density double edge triggered, (DET) flip-flop. The proposed DET flip-flop is implemented using lesser number of transistors as compared to other state of the art double edge triggered flip-flops designs. Simulation at 250MHz frequency using 180nm/1.8V CMOS technology with BSIM 3v3 parameters, the proposed design shows an improvement of upto 58.63%, 55.7%...
There is a growing demand for high-performance, low-power systems, particularly in portable devices. New approaches to design are needed in technologies with feature sizes of 90 nm and below to reduce leakage power and to deal with process variations, which force designers to use increasingly conservative delay estimations. This paper presents a variable clock generator for a conventionally-designed...
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