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This paper proposes the algorithm and its hardware architecture of a new CABAC-based parallel arithmetic entropy coder for on-chip large-scale parallel H.264 video coders. The proposed entropy coder partitions syntax elements into three independent groups according to their semantic dependencies, and processes them in three parallel threads, each of which is implemented as a fully pipelined hardware...
A System-on-Chip Design of VLD (Variable Length Decoder) in multi-standard video decoder is proposed in this paper. Our design supports all the popular video compression standards, e.g. MPEG-1, MPEG-2, MPEG-4, H.264, AVS, RealVideo. Benefit from its low power, the design is especially suitable for wearable multimedia applications. Simulation results show that the whole design takes an area of 1.04mm2,...
This paper introduces a low complexity VLSI hardware architecture for entropy coding with increased throughput, based on the study of the statistical properties of the context-based adaptive variable length coding (CAVLC) in AVC/H.264. These enhanced designs are due to the results of the statistical analyses, in which better symbol length prediction was achieved by breaking the recursive dependency...
This paper describes our techniques to design the intra-prediction of AVS encoder for HDTV applications. The whole design is optimized in both the algorithm and architecture levels. On the algorithm level, since the Plane mode is the most area-costly one, it is temporarily ignored. And SATD is lastly chosen as mode decision to balance the hardware implementation with performance of Rate and Distortion...
In A VS-P2 video compression standard, similar to MPEG-2, entropy coding firstly assembles two dimensional coefficients of each block into a sequence of (Run, Level) combinations serially. As we know, such the serial run-length method is usually undesirable for hardware accelerator and thus, this paper proposes an efficient parallel algorithm to Run-Length Coding, which can determine the (Run, Level)...
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