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Rapidly evolving markets and application demands of digital consumer electronics are pushing more functionality to software, increasing also requirements for memory capacity of systems. There have been efforts to reduce the need for memories by for example compressing the program code and thus also program memory footprint. We have previously introduced an effective code compression scheme, and in...
A System-on-Chip Design of VLD (Variable Length Decoder) in multi-standard video decoder is proposed in this paper. Our design supports all the popular video compression standards, e.g. MPEG-1, MPEG-2, MPEG-4, H.264, AVS, RealVideo. Benefit from its low power, the design is especially suitable for wearable multimedia applications. Simulation results show that the whole design takes an area of 1.04mm2,...
Inductive and capacitive coupling are responsible for slowing down signals. Existing bus encoding techniques tackle the issue by avoiding certain types of transitions. This work proposes a codeword generation method for such techniques that is scalable to very wide buses. Experimentation on a recent encoding technique confirms that the conventional method is limited to 16-bit bus while the proposed...
A new scheme of test data compression, namely equal-run-length coding (ERLC) scheme is presented, which is based on run-length. It first considers both types of runs of 0's and 1's, then it further explores the relationship between two consecutive runs on the basis of the traditional characteristic of run coding which uses shorter codeword to represent longer symbol (run-length). This scheme uses...
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