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The ITU-T H.264/MPEG-4 Part 10 Advanced Video Coding standard provides a reduction up to 50% of the bitstream rate if compared to previous standards. Among the innovation presented we should highlight the CABAC entropy coding (Context-based Adaptive Binary Arithmetic Coding), which shows a reduction of 9% to 14% in the bit-stream rate, when compared to the CAVLC basic entropy coding. The strictly...
Real-time video compression applications such as Digital Video Camera (DVC), Television Studio Broadcast, and Surveillance video utilize the H.264/AVC video encoder in intra-only encoding mode. The H.264/AVC standard supports multiple intra-prediction modes to reduce spatial redundancy in the video frame. The intra-prediction process for a current pixels block requires the reconstructed pixels from...
Rate control (RC) techniques play an important role for interactive video coding applications, especially in video streaming applications with bandwidth constraints. In this paper we propose a new BU-level rate control algorithm with ROI support and the associated architecture for H.264 and AVS by exploiting a new predictor model to predict the MAD value and target bits for hardware realization. The...
This paper presents a new error concealment algorithm, which is suitable for the H.264/AVC coding standard and the hardware implementation. This algorithm can be dividing into two major categories. In the spatial domain, we use the reliable neighboring pixel values with edge detection method to conceal all the lost pixels in the block. In the temporal domain, we propose a variable block size error...
This paper presents a fast H.264 intra frame encoder that processes an HD720p size video at 30 fps with the operating clock frequency of 40 MHz. The low clock frequency is achieved by a novel intra prediction schedule that employs pipelining of the 4 times 4 predictions and the early termination of 16 times 16 prediction. The pipelining is achieved by the optimal processing order for 4 times 4 predictions...
In this paper, we present an efficient H.264 / AVC intra 16times16 frame coder system. The system achieves real-time performance for video conference applications. The INTRA 16times16 is composed by intra 16times16 prediction, integer transform, quantization AC, inverse quantization AC, quantization DC, hadamard, inverse quantization DC, and inverse integer transform. The proposed hardware is implemented...
This paper proposes a high performance hardware architecture design for the H.264/AVC CAVLC encoder. The proposed architecture can make a realtime process for 1920 times 1080 @ 30p. With the synthesis constraint of a 114 MHz clock, the hardware cost of the proposed design is 7389 gates based on SS65LP 65 nm technology.
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