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When the flip-chip packaging has been moving to the lead-free, fine-pitch and high-current-density packaging, the flip chip with copper-pillar-bump interconnects can provide a solution to this need. However, this package during the thermal cycling test (TCT) still suffers the reliability problems such as delamination at the Cu low-k materials or at the interface between the UBM (under bump metallurgy)...
Based on the elastic-plastic model, two-dimensional finite element analysis was used to analyze the Air-Gap Cu interconnects thermal stress behaviors. Firstly, the stress evolution with the Air-Gap interconnect formation process steps was studied. Then, two Air-Gap types of Cu interconnects, with Air-Gap in the metal line level or extending to via level, combined with three different dielectrics were...
With the most popular electronics products being the slimmest ones with the highest functionality, the ability to thin, stack and interconnect chips is becoming more important. One method to accomplish this is by using the through silicon via (TSV). This is a means of electrical connection in 3D stacked devices that saves space and shortens the electrical interconnect length, improving electrical...
We reported the material properties, that we use in the numerical analysis, controls the quality of the analysis result directly in our previous paper. In this paper, we focus on the optimization of underfill for the high density packaging such as consumer electronics devices. We report the methodology to optimize the underfill properties through some parameter studies with numerical analysis. It...
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