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Sigma-Delta Analog-to-Digital converter (ADC), is widely used in portable electronic products. An operational transconductance amplifier (OTA) is one of the most important components of this ADC. This paper reports a new design of low power fully differential OTA. In this design authors have used adaptive biasing technique and DC gain enhancement technique for improving design parameters as compared...
A highly efficient approach to improve PSRR behavior of Kuijk BGR topology is derived though small signal transfer function analysis and, a BGR circuit has been designed and fabricated on standard 0.5μm CMOS technology to verify this method. This thought greatly relieves the trade-offs of BGR circuit design among power consumption, PSRR performance, area and etc.. This BGR circuit consumes 3μA current...
A low power linearity-ratio-independent DAC for ΔΣ data converters is proposed in this paper. By using a gain-boosted sub-threshold inverter as an amplifier, circuit power consumption is decreased significantly. The sensitivity of the differential DAC output linearity on circuit mismatches is reduced by using mutually-referred inputs. In a 0.13um CMOS technology, Monte-Carlo analysis and transistor-level...
Asynchronous circuits are well known for their intrinsic robustness to process, voltage and temperature variations. Nevertheless, in some extreme cases, it appears that their robustness is not sufficient to guarantee a correct circuit behavior. This limitation, which is caused by an analog phenomenon, appears when the transition slopes in input of C-elements become very slow. This paper describes...
A new frequency compensation technique for low-power, area-efficient multistage amplifiers is introduced in this work. By utilizing active capacitors to realize the compensation network in a nested way, two inverting gain stages can be used as the second and third gain-stages. The proposed scheme reaches better bandwidth-to-power and slew-rate-to-power performances comparing to the ever published...
Three dimensional memory systems has been argued as a potential pathway in solving the ever growing difference between comparative speeds of CPU and memory systems. In this paper, we describe a three-tier, three-dimensional SRAM macro that has been designed and fabricated in a 0.18 um FD-SOI CMOS technology. 3D stacking is found to improve wire latency as compared to planar memory structure although...
This paper discusses the design of a 60 GHz low noise amplifier (LNA) using a standard low power SOI CMOS process from ST Microelectronics. First, we outline the technology as well as the mm-wave design challenges. Using recent work on coplanar waveguide (CPW) modeling, we describe how it's possible to use parametric, 3D electromagnetic simulation to complete or replace analytical models of on-chip...
This paper describes a comparative analysis between two topologies of operational amplifiers to design a 40 MS/s 12-bit pipeline analog to digital converter (ADC). The analysis includes AC and transient simulation to select the proper topology. This ADC is implemented in a 0.35 mum AMS CMOS technology with 3.3 V single power supply. The capacitors and selected operational amplifiers were scaled for...
Class D amplifiers are becoming the most feasible solution for embedded audio application. However, distortions due to the non-linear nature of switching stage are the main drawback for this amplifier topology. This paper discusses the design and implementation of high fidelity audio class D using sliding mode control scheme. This design method proves to be a cost effective solution for industrial...
Advances in micromachining technology can facilitate the integration of SAW (Surface Acoustic Wave) devices and CMOS circuitry on IC scale substrate for Monolithic fabrication. The optimal design and performance of these filters can be reached by using new Smart materials. The key component in the structure of the SAW device is the piezoelectric materials used which depends mainly on some important...
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