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TSV failures due to manufacturing defects and thermal-induced latent defects result in yield and reliability issues in 3D-ICs. Recent work has shown different temperature mitigation techniques and fault tolerant architectures for 3D-ICs. It is known that TSVs are effective in reducing temperature by providing thermal conductivity. This is the first work that jointly considers temperature mitigation...
Virtual Coordinate (VC) based algorithms do not use physical coordinates for addressing, and thus possess many advantages for large scale sensor networks. They rely on the validity of VCs of nodes. VCs are affected by events such as node failures which are unpredictable and inevitable in WSNs. This degrades the performance of the algorithms and may even reduce overall life of the network. A distributed...
This paper proposes a distributed computing architecture using the P2P paradigm. Our proposal gathers the peers into markets according to their computational resources. Each market is arranged in an N-tree and the trees are linked by a Bruijn graph. The tree topology allows efficient searching of available resources in a specific market, while Bruijn provides good scalability as search complexity...
In this paper a BISR architecture for embedded memories is presented. The proposed scheme utilises a multiple bank cache-like memory for repairs. Statistical analysis is used for minimisation of the total resources required to achieve a very high fault coverage. Simulation results show that the proposed BISR scheme is characterised by high efficiency and low area overhead, even for high defect densities...
Networks on chips (NoCs) provide a mechanism for handling complex communications in the next generation of integrated circuits. At the same time, lower yield in nano-technology, makes self repair communication channels a necessity in design of digital systems. This paper proposes a reliable NoC architecture based on specific application mapped onto an NoC. This architecture is capable of recovering...
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