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This paper presents a low-power, variable block-size and irregular LDPC decoding. Our proposed LDPC decoder uses nanometer technology running the well-known TDMP and SMSA decoding algorithm. We further improved the design with pipeline structure, parallel computation and without any memory unit. Therefore, we can utilize only one routing network to route three different block-size data. The prototype...
This paper presents an FPGA implementation for LDPC codes performance simulation. The goal is for fast evaluation of LDPC code to investigate the error floor. The hardware evaluation platform features by fast simulation speed and high precision. The construction of the platform is described. The critical modules designed in the platform such as LDPC encoder, decoder, and AWGN noise generator are presented...
To cut down the hardware implementation cost this paper presents an efficient method to construct large girth Quasi-Cyclic low density parity check (QC-LDPC) codes. The row groups are paired two times the row weight, which has the complexity as compared to the connection of individual columns and rows. The complexity of directing within groups estimates on the transposition employed to connect rows...
Non-binary LDPC codes are now recognized as a potential competitor to binary coded solutions, especially when the codeword length is small or moderate. More and more works are reported with good performance/complexity tradeoffs, which make non-binary solutions interesting for practical applications, such as 4G-wireless systems or DVB-like systems. In this paper, we show that proposing non-binary LDPC...
In this paper, we construct the cyclic block-type low-density parity-check (CB-LDPC) codes for low complexity hardware implementation. The CB-LDPC code, which is a special class of quasi-cyclic LDPC (QC-LDPC), has an efficient encoding algorithm due to the simple structure of their parity-check matrices. A distribution of irregular parity-check matrix for the CB-LDPC is developed so that we can obtain...
The error-correcting performance of low-density parity check (LDPC) codes, when decoded using practical iterative decoding algorithms, is known to be very close to Shannon limits in the asymptotic limit of large blocklengths. A substantial limitation to the use of finite-length LDPC codes is the presence of an error floor in the low frame error rate (FER) region. This paper develops two methods, a...
Layered approximately regular (LAR) low-density parity-check (LDPC) codes are proposed, with which one single pair of encoder and decoder support various code lengths and code rates. The parity check matrices of LAR-LDPC codes have a "layer-block-cell" structure with some additional constraints. An encoder architecture is then designed for LAR-LDPC codes, by making two improvements to the...
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