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A 6-bit 1 GS/s single-channel pipeline ADC using an incomplete settling concept is presented. A background sampling-point calibration is proposed to adjust MDAC sampling point so that low gain and low bandwidth opamp can be utilized to conserve power. The prototype ADC in 65-nm CMOS process exhibits an INL of 0.76/ 0.68 LSB and a DNL of 0.72/ 0.68 LSB. Its ENOB is 5.25 bits at Nyquist input...
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