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The performance and reliability of 3-D NAND cells fabricated by TCAT (Terabit Cell Array Transistor) technology have been improved significantly via a damascened metal gates and a controlled offset between BL contact and select transistor. The damascened metal gate providing sufficiently low resistance is achieved by adopting a novel metal process. Highly suppressed disturbance property is achieved...
Power gating is an effective low-power design technique and is the most widely adopted leakage current reduction solution. In this project, we evaluate the effectiveness of power gating in 22 nm CMOS and analyze the impacts of the Positive/Negative Bias Temperature Instability (PBTI/NBTI) phenomenon on the power gating technique. We also estimate the actual temperatures of power gated circuits and...
Stress induced leakage current (SILC) has been observed on non-optimized high-K (HK) and metal-gate (MG) transistors. Large NMOS PBTI degradation and correlation to SILC increase on such gate stack is a result of large trap generations in the bulk-HK. This poses a long term reliability concern on product standby power and can limit the operating voltage if not suppressed. On an optimized HK+MG process,...
Grid-connected PV systems must withstand high voltage bias in addition to harsh environmental conditions. High leakage currents can lead to electromigration and degradation, and thus become important issues for reliability and safety. This paper describes high voltage bias testing of thin-film PV modules in hot and humid conditions in Florida. Sudden rise in RH caused by sudden drop in temperature...
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