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Stress induced leakage current (SILC) has been observed on non-optimized high-K (HK) and metal-gate (MG) transistors. Large NMOS PBTI degradation and correlation to SILC increase on such gate stack is a result of large trap generations in the bulk-HK. This poses a long term reliability concern on product standby power and can limit the operating voltage if not suppressed. On an optimized HK+MG process,...
NBTI has been extensively studied to understand physics of degradation in recent years. However, little has been done to find out the lifetime distributions of NBTI at both transistor and product level, which are important in reliability prediction and improvement. In this paper, Monte-Carlo simulation is carried out to study the NBTI lifetime distribution at transistor level. Lognormal distribution...
A non-classical device structure namely self-aligned quasi-silicon-on-insulator (SOI) metal-oxide semiconductor (MOS) field-effect transistor with pi-shaped semiconductor conductive layer (SA-piFET) is presented, seeking to improve the performance and upgrade the reliability of the SOI-based devices. Designed to equip with a SA single crystal silicon channel layer, plus a natural source/drain (S/D)...
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