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The architectural power intent of a design defines the intended global power states of a power-managed integrated circuit. Verification of the implementation of power management logic involves the task of checking whether only the intended power states are reached. Typically, the number of global power states reachable by the global power management strategy is significantly lesser than the possible...
Networks on chips (NoCs) provide a mechanism for handling complex communications in the next generation of integrated circuits. At the same time, lower yield in nano-technology, makes self repair communication channels a necessity in design of digital systems. This paper proposes a reliable NoC architecture based on specific application mapped onto an NoC. This architecture is capable of recovering...
In this paper we propose a set of different configurations of failure recovery schemes, developed for network-on-chip (NoC) based systems. These configurations exploit the fact that communication in NoCs tends to be partitioned and eventually localized. The failure recovery approach is based on checkpoint and rollback and is aimed towards fast recovery from system or application level failures. The...
Due to the growth of both design complexity and the number of gates per pin, functional debugging has emerged as a critical step in the development of a system-on-chip (SOC). Traditional approaches, such as system emulation and simulation, are becoming increasingly inadequate to address the system debugging needs. Design simulation is two to ten orders of magnitude slower than emulation and, thus,...
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