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A novel scheme for reducing the test application time in accumulator-based test-pattern generation is presented. The proposed scheme exhibits extremely low demand for hardware. It is based on a decoder whose inputs are driven by a very slow external tester. Experimental results on ISCAS benchmarks substantiate a test-time reduction of 75%-95% when compared to previously published test-set embedding...
This paper considers an alternative strategy to speed up the circuit simulation. This strategy considers characteristics of simulator users' behaviors and involves two techniques, the incremental simulation and simulation-on-demand (SOD). These techniques are implemented in an "Interactive Simulation Environment" to dramatically accelerate the simulation speed in most practical cases. Also,...
The model of an online multitape Turing machine is generalized by adding a bounded number of repositioning operations to the shift repertoire. It is proved that any such limited random access Turing machine can be effectively replaced by an equivalent conventional Turing machine which operates in the same time. This result yields simplified proofs and extensions of several results in the literature.
It is generally recognized that asynchronous operation of logic networks offers specific advantages over synchronous operation controlled by a central clock when the network is subject to large or widely varying inter-module propagation delays. In this paper we characterize several previously described techniques for achieving asynchronous operation by a single model. Essential to the model is the...
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