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The performance of router directly impacts the Network-on-Chip (NoC) performance. This paper focus on developing efficient microarchitecture of allocator in the router and proposed matrix-diagonal allocator with high matching quality and low packets latency. The allocator, taking advantage of the fact that each element in the diagonal doesn't share the same row or column, includes matrix-diagonal...
A virtual channel (VC) calculation algorithm for wormhole-switched on-chip networks is proposed. Traditionally, the virtual channels were allocated uniformly, which results in a waste of area and power. To remedy this situation, based on the queuing theory, we propose a router analytical model. Using this model, the proposed algorithm calculates the bandwidth usage at each router in the network according...
The virtual channel flow control approach provides an efficient way for the high throughput of the on-chip routers. However, allocating the virtual channels (VCs) statically results in a waste of the area and energy consumption. To remedy this drawback, we propose a novel dynamic virtual channel architecture (DVCA) in this paper. By inspecting the physical link state and speculating the packet transferring,...
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