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A new low-jitter polyphase-filter-based frequency multiplier incorporating a phase error calibration circuit to reduce the phase errors is presented. Designing with a multiplication ratio of eight, it has been fabricated in a 0.13-mum CMOS process. For input frequency of 25 MHz, the measured jitter is 2.46 ps (rms) and plusmn9.33 ps (pk-pk) at 200-MHz output frequency, while achievable maximum static...
High frequency/speed designs still predominantly use microstrip lines on relatively cheap FR-4 substrates, despite their relatively poor high frequency performance. One good alternative is to use CBCPW lines (conductor backed co- planar waveguide). Compared to CBCPW, microstrip lines are more susceptible to interference (EMI) and can more easily generate interference themselves. We have designed a...
This paper is on the study and analysis of the effects of corner conditions and post-layout simulations performed on a single-ended inductively degenerated common-source (CS) cascode LNA at nominal 2.14 GHz frequency. 2.14 GHz is the center frequency of the WCDMA reception range of 2.11 GHz to 2.17 GHz. This paper gives detailed explanation on the reasons for the behavior of the LNA under extreme...
A high intercept points, cost-effective, and power-efficient switching FET double balanced mixer (DBM) is reported. The Switching FET DBM demonstrated in this work offers input intercept points (IIP3) and conversion loss typically 44 dBm and 8.5 dB respectively with 15 dBm LO power for the frequency band (RF: 900-2150 MHz, LO: 850-1950 MHz, IF: 50-200 MHz). The measured interport isolation is typically...
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