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In this paper, compact memory strategies for partially parallel Quasi-cyclic LDPC (QC-LDPC) decoder architecture are proposed. By compacting several adjacent rows hard decisions and extrinsic messages into one memory entry, which not only reduces the number of memory banks for hard decisions, but also facilitates multiple data accesses per clock cycle, the throughput of the decoder is increased. We...
This paper simplifies the chase decoding algorithm for TPC codes for a particular modulation scheme (BPSK). Without reducing the decoding performance, the multiplication of the new algorithm is 33% of the original algorithm. The access algorithm of receiving matrix [R] is also optimized, and the access time of receiving matrix [R] is reduced to 3%. Finally, the 800M bps TPC decoder was implemented...
A novel scheme for reducing the test application time in accumulator-based test-pattern generation is presented. The proposed scheme exhibits extremely low demand for hardware. It is based on a decoder whose inputs are driven by a very slow external tester. Experimental results on ISCAS benchmarks substantiate a test-time reduction of 75%-95% when compared to previously published test-set embedding...
The computing power of microprocessors has exponentially increased in the past few decades, so the support to compute intensive multimedia applications has increased too. With such improved computing power, memory subsystem deficiency becomes the major barrier to support video decoder on the Digital Signal Processor (DSP). H.264/AVC becomes the next generation of video codec for embedded systems....
Porting MP3 decoder effectively on a given hardware platform ADSP-BF533 EZ KITLITE is discussed in this paper [1]. Data structure layout, proficient data placement and data memory/cache handling for porting MP3 decoder are discussed. Hardware features and advanced instructions are availed for effective implementation of MP3 modules to reduce the MIPS. Results show MP3 decoder implementation consumes...
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