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While the CMOS analog circuits can be designed with the minimum-gate-length of the fabrication process in the alpha-power law MOSFET model, the length of a MOSFET gate has been chosen to be a larger scale than the minimum-gate-length in the conventional Shockleypsilas square model. In this paper, we describe a 6-b 100 MSPS CMOS current steering digital-to-analog converter (DAC) with the alpha-power...
The challenges of deriving early-adopter competitive advantage, even with fabless access to process technology, through leveraging features offered by the advanced, and possibly disruptive, process technologies in real SoC products, are outlined. A structured methodology for addressing these challenges, and bridging the gap between process and design, sufficiently early in the development cycle to...
We present a generic method for analyzing the effect of process variability in nanoscale circuits. The proposed framework uses kernel and a generic tail probability estimator to eliminate the need for a-priori density choice for the nature of circuit variation. This allows capturing the true nature of the circuit variation from a few random samples of its observed responses. The data-driven, non-parametric,...
Novel 3D stacked gate-all-around multichannel CMOS architectures were developed to propose low leakage solutions and new design opportunities for sub-32 nm nodes. Those architectures offer specific advantages compared to other planar or non planar CMOS devices. In particular, ultra-low IOFF (< 20 pA/mum) and high ION (> 2.2 mA/mum) were demonstrated. Moreover, those transistors do not suffer...
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