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In-house technology for digital beam position measurement is being developed for Indus-2 Synchrotron radiation source. FPGA based digital processing electronics is being designed to acquire the signal from 4-electrode BPM device using 4-channel ADC. These ADC will be calibrated by the spectrum analysis of the input signal. In this paper, High Speed Printed Circuit Board [PCB] will be designed using...
This paper proposes a fast lock data recovery method operating with the inaccurate and higher jitter reference clock such as the CR oscillator. The proposed circuit consists of a blind oversampling deserializer and a data recovery logic circuit. And this circuit decides the consecutive bits' number by the bit-boundary estimation. The estimation calculated only from the past 10 bit-transition timing...
In this paper we present an architecture for a software defined M-PSK (M=2, 4, 8) receiver which was prototyped to handle real world satellite signals of Eb/N0 up to 4dB for BPSK and QPSK and up to 6dB for 8-PSK using only 2 samples per symbol. This design supports symbol rates between 32kS/s and 10MS/s. We also present the BER curves of the demodulator designed and the approach we took to obtain...
The paper presents an efficient and parallel symbol timing recovery algorithm suitable for very high speed demodulator and easy to implement on FPGA platform. The proposed timing recovery algorithm has a dual feedback structure which makes up of frequency domain timing phase correction, first reported in Alternate Parallel Receiver (APRX), and parallel FIFOs based delete-keep algorithm. In the timing...
The wireless communication system used by an Unmanned Aerial Vehicle has special requirements. Two separate data streams are used, one for telemetry and control of the vehicle, and one for payload. The first stream is of relatively low data rate, but must be very robust. The second stream requires high data rate, but a best effort approach is acceptable. Real-time remote control usage mandates low...
In this paper we present the implementation of a FPGA based high data rate BPSK receiver specifically designed to withstand the high dynamics of airborne vehicles (i.e. aircraft, sounding rockets, satellites, etc.). The carrier recovery is implemented through a Costas loop, and a Gardner detector is used for the timing recovery. This architecture was chosen because it provides almost independent carrier...
The European X-ray Free Electron Laser experiment (XFEL) [1][2] at DESY in Hamburg will start in a few years and make possible new, impressive experiments. The whole system will require a very precise clock and trigger distribution, synchronous to the 1.3 GHz system RF-frequency, over distances of more than 3.4 km. Stockholm University in collaboration with DESY has developed a prototype for the timing...
The Project25 (P25) standard was developed to serve the communication needs of emergency workers and the public safety community. Using a software-defined radio structure for emergency radio standard within the framework of an RF ASIC/SoC like Texas Instruments (TI) low cost Digital RF Processor (DRPtrade) chip is an important step forward to help the public safety community reduce hardware costs...
An SoC framework is presented, comprising of a plug-and-play infrastructure where the system communication is abstracted from the processing elements. A software scheduler is used with a hardware modelling environment for latency analysis. Using the framework, an LTE uplink data channel (PUSCH) receiver design is shown to meet the stringent latency targets.
An analysis-based framework for the rapid development of a radio receiver for signals with unknown parameters is pro-posed, exploiting the reconfiguration capabilities of FPGAs. The framework guides a non-expert user through the process of signal classification and FPGA-based receiver implementation. System efficiency is traded off with implementation time in order to allow fast radio creation. A...
The significant problem of data dropouts in aeronautical telemetry due to multiple transmit antennas has escalated as transmit data rates have increased. A proposed solution of using a space-time coded signal can resolve these data dropouts at the expense of increased receiver complexity. This paper describes an implementation overview of an FPGA-based space-time coded telemetry receiver and the various...
Cooperative MIMO is a new technique that allows disjoint wireless communication nodes (e.g. wireless sensors) to form a virtual antenna array to increase bandwidth, reliability and/or transmission distance. It differs fundamentally from other MIMO communication since the signals received from each node have a relative timing and frequency offset due to the distributed nature of their transmitting...
The rate compatible punctured convolutional code (RCPC code) is an important module in Multi-band Orthogonal Frequency Division Multiplexing Ultra Wide Band (MB-OFDM-UWB) indoor positioning system introduced in this paper as a kind of useful channel coding to offer more protection against all kinds of channel noise under indoor channel environments. In this paper, RCPC code for MB-OFDM-UWB indoor...
Fast Fourier Transform (FFT) is the most basic and essential part of Software Defined Radio (SDR). Therefore, designing regular, reconfigurable, modular and low hardware complexity FFT computation block is very important. A single FFT block should be configurable for varying length FFT computation and also for computation of different transforms like DCT, DST etc. In this paper, the authors analyze...
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