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A CORDIC processor with three computation modes is designed. The design targets low power applications. A novel fine grain clock gating scheme is employed to reduce power. The design is mapped to two technology nodes, i.e., 350 nm and 65 nm, using a script-based, parameterizable ASIC/SoC flow that can be easily adapted for different designs and technologies for fast concept-to-silicon mapping. Power...
A streaming application, characterized by a kernel that can be broken down into independent tasks which can be executed in a pipelined fashion, inherently allows its implementation on a pipeline of Application Specific Instruction set Processors (ASIPs), called a pipelined MPSoC. The latency and throughput requirements of streaming applications put constraints on the design of such a pipelined MPSoC,...
This paper makes research on automatic gating clock technology in SoC clock network. Based on SoC1000 CPU core, analyze the characters of its inner time logic and combine ASIC physical design flow and method based on standard unit. This paper puts forward a clock network scheme based on precise credible time analysis. This method can greatly reduce SoC clock dissipation and at the same time, it can...
Microrobots were proposed more than 20 years ago but it has proven challenging to integrate a power system and actuators into some few mm3. There have been some attempts to create an autonomous mobile microrobot but any has been successful. Moreover, the proposed microrobots were simply mobile platforms incapable of sensing its environment and taking decisions. I-SWARM has been designed to be a real...
To bring the benefits of CMT to larger workloads, these systems had to scale beyond a single socket. Because CMT requires massive memory bandwidth to achieve adequate throughput performance, the challenge was to develop a coherency link and fabric that would allow performance to scale along with thread count in a multinode (that is, multisocket) system. In this article CoHub's coherency scheme, ASIC...
Summary form only given. Power reduction is becoming a critical design criterion for ASIC/SOC designers. Reducing both dynamic and leakage power is imperative to meet power budgets for portable devices as well as to ensure that the systems that these ASICs meet their packaging and cooling costs. In addition, the power of an ASIC has a significant impact on its reliability and manufacturing yield....
Multi-FPGA systems are a growing area of research. They offer the potential to deliver high performance solutions to general computing tasks, especially for the prototyping of digital logic. However, to realize this potential requires a flexible, powerful hardware substrate and a complete, high quality and high performance automatic mapping system. This paper discusses different aspects of multi-FPGA...
Output connections to out-of-chip devices in modern mixed-signal ICs represent a significant design problem due to the limited number of available pins (in not Ball Grid Array package) and to the common need of a frequency reduction, especially into systems that require an external System on Programmable Chip (SoPC). In this paper, an ASIC solution based on bi-synchronous FIFO structures for frequency...
An SoC ASIC is an integration of many complex components such as analog cores, digital cores, user defined logic, memories, etc. If not properly planed, lab validation of such an ASIC can be time consuming. This paper proposes a design for validation architecture that includes a built-in functional test for fast lab validation and system integration. The proposed scheme has been adopted in a 40 Gbps...
This paper presents an effective design of a asynchronous FIFO circuit for multiple asynchronous clocks data transmission. The dual synchronization and gray code are proposed. According to experiments, the probability of metastability is reduced effectively. In the simulation the proposed circuits can operate at a clock rate of 256 MHz while in writing and 329 MHz in reading and is implemented in...
In this paper an H.264/AVC baseline profile encoder is proposed, designed to be implemented on the STMicroelectronics SPEAr customizable SoC family. Computational intensive modules, like motion estimation and compensation, have been implemented in hardware and prototyped on a Xilinx FPGA where they operate at the maximum frequency of 56.179 MHz. To gain a good adaptiveness for different aims, the...
In this paper, we provide an overview of our reprogrammable multi-clock distribution scheme. We present potential architectures using this scheme, information on controller requirements and the system's operating characteristics, including a skew and jitter study. We show that reference-based clocking provides a skew tolerant scalable solution that can re-route clocks using specially designed switch-points,...
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