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The time-triggered principle establishes and maintains a system-wide synchronized time-base by the local clocks of the device. The proposed concept of Time-Triggered Ethernet (TTE) guarantees the determinacy of time-critical message for avionics and safety-critical systems. This paper presents an algorithm based on path-hop of tasks to generate a rational scheduling timetable to ensure is free of...
Software-Defined Network architecture offers network virtualization through a hypervisor plane to share the same physical substrate among multiple virtual networks. However, for this hypervisor plane, how to map a virtual network to the physical substrate while guaranteeing the survivability in the event of failures, is extremely important. In this paper, we present an efficient virtual network mapping...
The NoC synthesis defined as the generation of a Network On Chip (NoC) architecture optimized for a specific application subject to various constraints, is a very important step in ASIC design methodologies. In this work we will present a new NoC synthesis method based on linear programming. We will apply our algorithm on multimedia coregraphs like 263 enc MP3 dec, MPEG4 and H.264. We reduce the complexity...
This paper describes a new path computation model in Multi-protocol Label Switching (MPLS) and Generalized MPLS (GMPLS) networks. It introduces a path computation element (PCE), which is functionally separate from label switching routers (LSRs). The Path Computation Element (PCE) is an entity that is capable of computing a network path or route based on a network graph, and applying computational...
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