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In this paper, a CMOS ultra-wideband (UWB) pulse generator is designed in IBM 90 nm technology for on-chip wireless interconnect applications. A UWB pulse is generated using the triangular pulse generation technique. The output pulse is OOK modulated according to data and each data bit is preceded by a reference pulse. A maximum data rate of 2.5 Gb/s with transmitted reference is achieved when the...
This paper presents a comparative study of three low-noise amplifiers for neural recording applications. The topologies are thoroughly analysed in terms of area, power consumption and noise performance. Further, the theoretical results are confirmed by simulations of transistor-level implementations in a 0.13μm CMOS technology at 1.2V supply voltage.
This paper demonstrates a 23.5 GHz double stage low noise amplifier using an innovative inter-stage matching technique. The same matching technique is also used at the output of the amplifier for the purpose of output matching. The circuit is designed in IBM .13 mum CMOS process and is simulated using cadence spectre. The simulated responses exhibit a forward gain of 20 dB at 23.5 GHz with a bandwidth...
This paper presents a directly modulated, 60 GHz zero-IF transceiver architecture suitable for single-carrier, low-power, multi-gigabit wireless links in nanoscale CMOS technologies. This mm-wave front end architecture requires no upconversion of the baseband signals in the transmitter and no analog-to-digital conversion in the receiver, thus minimizing system complexity and power consumption. All...
This paper presents the design of an active-RC filter with variable bandwidth and channel-selectivity characteristics for wireless communication applications. The topology of this filter is the 5th-order low pass type. The 3-dB bandwidth is programmable at 10, 20 and 40 MHz. The filter is fabricated in a 0.13-mum CMOS technology and dissipates 13.2 mW for a supply voltage of 1.2 V.
This paper presents the design and the measurement results of a 3-5-GHz down-converter fabricated in a 90-nm CMOS technology. The circuit consists of a single-ended resistive-feedback low-noise amplifier and two I/Q double-balanced mixers. A transformer-based on-chip single-ended-to-differential conversion allows gain and noise performance to be optimized at a very-low power. A post-layout stability...
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