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We design PDLL that has a PLL and a DLL with different roles. The DLL, which is used for phase compensation, is digital with low power consumption. The PLL, which is used for jitter reduction, is a charge-pump type with dual KVCO and self-mode-shifting scheme, using an unregulated power supply for flexibility in operating range. Powering the PLL with an unregulated power supply is made possible by...
Notice of Violation of IEEE Publication Principles"Jitter Analysis of a Mixed PLL-DLL Architecture,"by M. Sayfullah, B. Roland, A.L. Scholtz,in the Proceedings of the International Conference on Electrical and Computer Engineering, 2008. ICECE 2008, pp. 750-754After careful and considered review of the content and authorship of this paper by a duly constituted expert committee, this paper...
A low-phase-noise 1-2 GHz clock multiplier is configurable as PLL or DLL. Starting in PLL-mode, a lock-detect circuit switches the circuit to DLL and simultaneously reconfigures the loop filter. Upon loss of lock the circuit automatically falls back to PLL-mode. The number of stages in the VCO/delay line is programmable to 8-10-12-14-16, implementing band selection with modest tuning gain KVCO. Multiplication...
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