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The increasing system complexity of FPGA-based hardware designs and shortening of time-to-market have motivated the adoption of new designing methodologies focused on addressing the current need for high-performance circuits. High-Level Synthesis (HLS) tools can generate Register Transfer Level (RTL) designs from high-level software programming languages. These tools have evolved significantly in...
This paper describes the joint effort of the two FP7 EU projects CLERECO and MoRV toward the definition of an extended reliability information exchange format able to manage reliability information for the full system stack, from technology up to the software level. The paper starts from the RIIF language initiative, proposing a set of new features to improve the expression power of the language and...
The digital rocket-ground signal detection and analysis system is mainly used to remote and local real-time detect and acquire the signals from the key equipments of the control system of the carrier rockets. As a supporting product of the launch vehicles, this system has strict reliability requirements for the hardware and software. With the design of a multi-channel, integrated, real-time detection...
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