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All Programmable System-on-Chip (APSoC) devices are designed to provide higher overall system performance and programmable flexibility at lower power consumption and costs. Although modern commercial APSoCs offer a plethora of advantages, they are prone to experience Single Event Upsets. We investigate the impact of using different system architectures on an APSoC in the overall system failure rate...
We investigate the impact of using different system architectures on an APSoC, such as memory organization, communication schemes and by using hard- and soft-cores in the same context, in the final system failure rate.
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