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Technology scaling leads to burn-in phase out and increasing post-silicon test complexity, which increases in-the-field error rate due to both latent defects and actual errors. As a consequence, there is an increasing need for continuous on-line testing techniques to cope with hard errors in the field. Similarly, those techniques are needed for detecting soft errors in logic, whose error rate is expected...
The Niagara2 CMT system-on-chip incorporates many design-for-test features to achieve high test coverage for both arrays and logic. All the arrays are tested using memory built-in-self-test. This is supplemented with scan-based testing. Logic is tested with standard ATPG for slow-speed defects and extensive use of transition test, along with logic built-in-self-test for the SPARC cores, for at-speed...
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