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This paper presents a capacitor mismatch calibration technique in multibit discrete-time sigma-delta (ΣΔ) modulators based on a capacitor error model, including nonideal integrator gain errors. This model enables the compensation of mismatch-induced nonlinear memory errors in conversion using a simple flnite impulse-response structure. Single-bit pseudorandom noise (PN) is utilized to identify the...
A low-voltage 5th-order continuous-time ΣΔ modulator for a universal mobile TV receiver is presented. A unique feature of the proposed modulator is the blocker filtering provided using a 3rd order notch filter employing frequency dependent negative resistance (FDNR). The noise added by the FDNR is shaped. The modulator employs 3-level switched-capacitor DAC in the feedback. It has been implemented...
A true low voltage - low power ΔΣ modulator is presented. The power supply is only 1.5V. The power dissipation is only 100 μW. The modulator is a second order single loop topology implemented with the switched opamp technique. Consequently no voltage multiplication of any kind is needed. The chip is implemented in a 0.7μm CMOS process with normal threshold voltages. The measured dynamic range in the...
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