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The technology of 3D IC integration is highly probable to achieve the demand for high performance, better reliability, miniaturization and lower-priced portable electronic products. Since the through silicon via (TSV) is the heart in 3D IC integration architectures, the reliability issues of TSV interconnects should be extremely concerned. Due to the large thermal expansion mismatch among the Cu,...
This paper investigates two key aspects of thermomechanical reliability of through-silicon vias (TSV) in 3D interconnects. One is the piezoresistivity effect induced by the near surface stresses on the charge mobility for p- and n- channel MOSFET devices. The other problem concerns the interfacial delamination induced by thermal stresses including the pop-up mechanism of TSV with a `nail head'. We...
This study assesses the reliability life of 3D chip stacking packaging developed by the Industrial Technology Research Institute (ITRI). The simulation results show that the trends of stress of through silicon via (TSV) structures with different chip stacking numbers are nearly constant during thermal stress analysis. Therefore, the simplified two-layer chip stacking model is adopted to analyze the...
Through-Silicon Vias (TSVs) have recently aroused much interest because it is a key enabling technology for three-dimensional (3-D) integrated circuit stacking and silicon interposer technology. In this study, a 3-D 1/8th symmetrical nonlinear finite element model of a stack die TSV package was developed using ANSYS finite element simulation code. The model was used to optimize the package for robust...
Multi-physics characterization of multi-layered stacked through silicon vias (TSVs) is performed based on the hybrid time-domain finite element method (FEM), with most temperature-dependent material parameters treated appropriately. Using our developed algorithm, numerical computation is carried out so as to capture transient electro-thermo-mechanical responses of different TSV geometries injected...
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