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In this paper, we present a new architecture forFPGA checkpointing along with an efficient mechanism. Wethen provide a static analysis of original HDL source code toreduce the cost of hardware for checkpointing functionality. Ourevaluations show that with the proposals, checkpointing hardwarecauses small degradation in maximum clock frequency (less than10%). The LUT overhead varies from 14.4% (Dijkstra)...
This work describes the designing of a Graphics Processing unit that deals with image processing. Graphics Processing Unit (GPU) is an important factor when it comes to large computing. Images and videos that are having large data can be processed efficiently in GPU by exploiting its feature of parallel execution. Digital image processing implemented on hardware provides higher processing speed and...
Creativity of a computer engineer is always sought after due to the increasing demands in the production of embedded systems worldwide. To ensure teaching of computer architecture subject as interesting as possible to computer engineering students, a simulation software for understanding typical computer processors was introduced. For hardware realization, a hardware description language was also...
Hardware design with FPGAs can be a daunting task, even for experienced engineers. Even with sophisticated tools and improvements in high-level language to gates approaches, an engineer can expend significant effort simply implementing the design. Often, when the design is evaluated on the FPGA, the performance may not be what was expected. As a result, an engineer may go back and augment the design...
Rapid HDL is an object oriented software library for scripting the generation of synthesizable Verilog. A fully functional customized microprocessor is defined and automatically synthesized for an FPGA from an XML specification file. Using a library of blocks, a microprocessor fabric is defined in XML. Control states specify the connections between the fabric blocks during microprocessor operation...
In this work, we present Odin II, a framework for Verilog Hardware Description Language (HDL) synthesis that allows researchers to investigate approaches/improvements to different phases of HDL elaboration that have not been previously possible. Odin II's output can be fed into traditional back-end flows for both FPGAs and ASICs so that these improvements can be better quantified. Whereas the original...
Flexible Application Specific Instruction set Processors (ASIP) are starting to replace monolithic ASICs in a wide variety of fields. However the construction of an ASIP is today associated with a substantial design effort. NoGAP (Novel Generator of Micro Architecture and Processor) is a tool for ASIP designs utilizing hardware multiplexed data paths. One of the main advantages of NoGAP compared to...
This article first proposes a problem encountered in the project and the feasibility of solving it using FPGA. Then speaks the theory of velocity planning with trapezoidal curve and control strategy. Final details the implement of hardware and software of the step motor controller IP core, include the implement of hardware logic and the code writing of drive file and the package of driven functions...
Phonetic search represents a new area in information retrieval. Its goal is to search texts for all words that have the same pronunciation as the word heard and written by the user. The user is assumed to be a foreigner who uses in general a different alphabet and different transcription rules. With rapid advances in programmable hardware (FPGA), a natural idea would be to use FPGA-implementations...
Hardware acceleration uses hardware to perform some software functions faster than it is possible on a processor. This paper proposes to optimize hardware acceleration using path-based scheduling algorithms derived from dataflow static scheduling, and from control-flow state machines. These techniques are applied to the MIPS-to-Verilog (M2V) compiler, which translates blocks of MIPS machine code into...
DCT/IDCT finds potent application in the field of image and signal processing. In this paper, we concentrate on a novel five stage pipelined implementation, which consumes less power. The design uses Verilog HDL and is simulated in Modelsim 6.3b. Matlab is used to generate the data in binary format which serves as the input data and cosine values for computing 1D DCT/IDCT in HDL. There are other low...
The adaptive arithmetic codec is one of the key algorithms of JPEG2000 standard. Its complexity of implementation is relatively high. In this paper Handel-C language is used as hardware description language to design the arithmetic decoder of JPEG2000. The design is debugged and synthesized under the Celoxica Design Kit. The experimental results show that we can implement arithmetic decoder to FPGA...
Nios II is the soft-core 32 bits RISC processor of the Altera Corporation which can be implied in its FPGA. Users can design their own peripherals accord with Avalon Bus specification in Nios II system. A new design method for plus width module (PWM) peripheral is presented, which is completed by Verilog HDL. Comparing to the common PWM module, this new PWM module use the hardware units (logic elements...
Low density parity check (LDPC) codes are the error-correcting codes which offer huge advantages in terms of coding gain, throughput and power dissipation. Error correction algorithms are often implemented in hardware in order to ensure fast processing. The hardware implementation of LDPC decoders using traditional hardware description language (HDL) based approach is a complex and time consuming...
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