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The complexity of formalizing the semantics of Verilog is significant. This presents an impediment when attempting to provide high assurance in the correctness of Verilog synthesis. This paper explores the use of higher-order transformation as a paradigm for implementing a synthesis system for a small subset of Verilog. The resulting system is capable of synthesizing net lists in the Xilinx Net list...
Due to increasing demand of new technology, the complexity of hardware and software consisting embedded systems is rapidly growing. Consequently, it is getting hard to design complex devices only with traditional methodology. In this contribution, I introduce a new approach of designing complex hardware with SystemVerilog. I adopted the idea of object oriented implementation of the SystemVerilog to...
The increasing complexity in the design of protocol based sequential digital systems such as USB3.0 and PCI express (PCIe), is leading to an increased time to market constraint. This paper introduces a UML based visual design approach to address this increased complexity in the design of IP as well as System-on-Chips (SoC). A hardware development method for USB3.0 device using the Unified Modeling...
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