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Reconfigurable system-on-a-chip(SoC) is an important trend of embedded system. It is not only to achieve a higher performance but also flexible enough. In this paper a new kind of reconfigurable system using SoP(System on a Package) technology is presented and a new kind of peripheral bus which is used to form a whole system architecture is proposed based on the reconfigurable system. Using this peripheral...
Based on the design of MIPS[1], an novel 32-bit CPU is proposed, whose structure is simple and efficient for image processing. The specially designed CPU can be embedded into video encoder or other multimedia processor, and work well, it can also be used to do DWT (digital wavelet transform) with only few instructions. Furthermore, we take good advantage of the same hardware model to implement more...
In this paper we propose a novel parallel hardware architecture for two binary matrix inversion and vector decoding algorithms, for hard Raptor decoder. We compare the achieved performance to a software based implementation in an embedded processor. We demonstrate the superiority of our proposed architecture in terms of performance (by a factor 12), power and energy dissipation (by a factor of 15)...
Embedded systems designers frequently avoid using floating-point computation because it is too costly to include a floating-point unit (FPU) in an embedded processor. However, the performance of software floating-point libraries can be lacking. Therefore we propose a fractured floating point unit (FFPU)-a hybrid solution using a mix of custom hardware instructions and software code. An FFPU is designed...
Although the use of floating point hardware in FPGAs has long been considered unfeasible or relegated to use only in expensive devices and platforms, this is no longer the case. This paper describes fully-fledged implementations of single-precision floating point units for a MIPS processor architecture implementation. These coprocessors take as little room as 6% of a medium-sized FPGA, while the processor...
This paper focuses on the application of Virtual Reconfigurable Circuit (VRC) design methodology and intrinsic evolution for the design of small sequential circuits and their implementation on a single programmable chip with an embedded hardcore processor. The evolutionary algorithm is developed in software that runs on the embedded processor. Fitness function is calculated using hardware architecture...
In this paper, we propose a self-reconfigurable platform which can reconfigure the architecture of DCT computations during run-time using dynamic partial reconfiguration. The scalable architecture of DCT computations can compute different number of DCT coefficients in the zigzag scan order to adapt to different requirements, such as power consumption, hardware resource, and performance. We propose...
Over the past decade, the consumer market has been flooded with variegated embedded devices that are progressively becoming cheaper, faster and more power-efficient. New applications are constantly appended into these devices. This work is aimed at emulating such devices using some benchmarks and observing the performance gains that can be achieved by modifications to the design of different hardware...
This paper proposes a parallel hardware architecture for image feature detection based on the scale invariant feature transform algorithm and applied to the simultaneous localization and mapping problem. The work also proposes specific hardware optimizations considered fundamental to embed such a robotic control system on-a-chip. The proposed architecture is completely stand-alone; it reads the input...
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