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A new low-power switched-capacitor integrator is proposed for high-resolution ΔΣ ADCs. Compared to the conventional switched-capacitor integrator, it achieves much lower power dissipation for the same noise specifications. To verify the effectiveness of the new integrator, and to compare it with the conventional one, a third-order delta-sigma modulator was simulated. A detailed comparison between...
This brief presents a hybrid analog-digital ΔΣ analog-to-digital converter architecture with a pseudodifferential integrator based on current-controlled oscillators (CCOs). Two oscillators driven by differential input signals and followed by digital counters are used to form a quantizer whose output is digitally integrated. This pseudodifferential circuit configuration reduces the relative quantization...
This paper presents a new two-stage cascade ΣΔ modulator architecture that uses inter-stage resonation to increase its effective resolution as compared to conventional cascades and avoids the need for digital filtering in the error cancellation logic. The combination of these two strategies, together with the use of unity signal transfer function in all stages, make the presented modulator highly...
A switched-capacitor low-distortion 15-level delta-sigma ADC is described. It achieves third-order noise shaping with only two integrators by using quantization noise coupling. It provides 81 dB SNDR, 82 dB dynamic range, and -98 dB THD in a signal bandwidth of 1.9 MHz. It dissipates 8.1 mW with a 1.5 V power supply (analog power 4.4 mW, digital power 3.7 mW). Its figure-of-merit is among the best...
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