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This paper presents an area efficient 10-bit, 40 MS/s SAR ADC. The design strategy to minimize the circuit area adopts the pipelined architecture. The 10-bit SAR ADC is divided into 4-bit (first stage) and 6-bit (second stage) SAR ADC. The two-stage pipelined structure achieves a reduction of the number of capacitors, which is the dominant source of the circuit area of SAR ADCs. To avoid the comparator...
The multiplying D/A converter stage with time-shifted correlated double sampling technique is analyzed. Comprehensive models for the residual error due to finite amplifier gain and the thermal noise power are derived; the settling behavior of such stages is presented. It is shown that the selection of the error storage/hold capacitance introduces tradeoffs with respect to noise, accuracy, and power...
An integrated readout circuit for Lab-on-a-Chip applications is presented. The overall system consist of a 640times480 array of capacitor sensors and actuators. Sensors detect dielectric permittivity variation thanks to dielectrophoresis (DEP) process. Usually for this kind of applications an off-chip analog-to-digital converter is used. As a consequence, the noise floor increases and high signal-to-noise...
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