The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
In this paper, a CMOS ultra-wideband (UWB) pulse generator is designed in IBM 90 nm technology for on-chip wireless interconnect applications. A UWB pulse is generated using the triangular pulse generation technique. The output pulse is OOK modulated according to data and each data bit is preceded by a reference pulse. A maximum data rate of 2.5 Gb/s with transmitted reference is achieved when the...
This paper presents a 40-Gb/s phase-locked clock and data recovery (CDR) circuit with 1:4 demultiplexer in IBM 90-nm CMOS technology. The CDR circuit incorporates an inductorless eight-phase LC voltage-controlled oscillator (VCO) and a quarter-rate bang-bang phase detector (PD). A novel inductorless eight-phase LC VCO including four LC oscillator cells is presented to generate the eight-phase outputs...
This paper introduces the 10 b 1 MS/s 0.5 mW SAR ADC with double sampling technique. It utilizes the double sampling technique to reduce power. The SAR ADC is implemented in CMOS 1P8M 65 nm technology and occupies 0.111 um2. The maximum sampling rate is 1 MS/s. The simulated SNDR and SFDR are 55.6 dB and 62.7 dB, respectively at input frequency of 484 kHz. Power consumption of the data converter is...
A low power architecture to extend the frequency range of quadrature clock is proposed. This architecture is based on a series of dividers. It can enhance the lower frequency limit of a Quadrature Voltage Controlled Oscillator (QVCO) clock to any arbitrarily small frequency. Based on the architecture a design is shown which enhances the low frequency range up to -90% of the center frequency, assuming...
This paper describes the fastest full-rate retiming circuit reported to date in any semiconductor technology. By combining low- and high-VT MOSFETs on the data and clock path, respectively, and CMOS-inverter based transimpedance amplifiers as low-noise, broadband preamplifiers, record speed is achieved with 1.2 V supply. The power consumption of the 81 GHz latch is only 9.6 mW. On-wafer measurements...
This paper reports on the design and implementation of a low-voltage, low-power Wake-Up circuit consisting on a Power-on-Reset module and a clock generator. No external components are used neither for the Power-on- Reset nor for the clock generation. The clock generator module is temperature compensated by applying a current limiting technique. The Wake-Up circuit has been fabricated in a 130 nm ultra-low...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.