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This paper presents a half-run RC5 cipher architecture with low power dissipation for transmission security of biomedical systems. The proposed architecture uses a resource-sharing approach utilizing only one adder/subtractor, one bi-directional barrel shifter, and one XOR with 32-bit bus width. Therefore, two data paths are switched through four multiplexers in the encryption/decryption procedure...
Advance Encryption Standard (AES), has received significant interest over the past decade due to its performance and security level. In this paper, we propose a compact 8-bit AES crypto-processor for area constrained and low power applications where both encryption and decryption is needed. The cycle count of the design is the least among previously reported 8-bit AES architectures and the throughput...
A new VLSI implementation for a 197-bit finite field multiplier using redundant representation is presented. The proposed design uses a simple module designed in domino logic as the main building block for the multiplier. We have used .18 mum CMOS technology from TSMC for our design. The final multiplier design was successfully simulated at a clock rate of 1.82 GHz. The proposed multiplier is at least...
This paper describes a design and implementation of low-power and high-speed security hardware cores for the advanced encryption standard (AES) and the secure hash algorithm (SHA1). We propose three register transfer level (RTL) circuit techniques, namely, application specific register reduction (ASRR), locally explicit clock enabling (LECE), and bus specific clock (BSC). LECE and BSC can be used...
Cheap passive radio frequency identification (RFID) tags operating in ultra high frequency (UHF) bands are fostering innovation in several field such as building access control, goods tracking and supply chains management. RFID transponders can also be coupled to tiny sensors, enabling non invasive monitoring of environmental and personal parameters. To ensure the privacy of highly sensitive data,...
This paper presents principles and results of dynamic testing of an SRAM-based FPGA using time- resolved fault injection with a pulsed laser. The synchronization setup and experimental procedure are detailed. Fault injection results obtained with a DES crypto-core application implemented on a Xilinx Virtex II are discussed.
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